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170 Threads found on edaboard.com: Synthesis Power
Hi all, I'm presently doing synthesis of a V code in DC. I had applied clock gating(combination) to the design. The dynamic power got increased by some reasons. It can be due to the area increase, but actually the power is supposed to get reused right? The slack after gating has been reduced. Can anyone suggest how to reduce my (...)
Perhaps you can code the function in HDL and do synthesis (using Synopsys Design Compiler for eg), then use report_power command to find the power consumption. Thanks.
I see it this way: The synthesis tool doesn't need to rewrite the code. POR is a hardwired feature that sets all registers unconditionally to zero on power-on. An asynchronous reset input of each register can optionally perform the same during operation. The result is however the same. More important than guessing about internal wiring details o
Hi everyone, Is there a way to connect multiple drivers to a single port in FPGA synthesis. Here is a sample code: ... signal out: std_logic_vector (7 downto 0); signal in1: std_logic_vector (7 downto 0); signal in2: std_logic_vector (7 downto 0); signal in3: std_logic_vector (7 downto 0); out <= in1; out <= in2; out <= in3; .
quite large question! well, personally, I never used the synthesis power plan, but always power planning-add stripes command and I clean up my floorplan manually before a double check in calibre or other DRC signoff tool. A good floorplan is made when: -minimum space lost between macros/rows, -macros placed in order to be close to (...)
Hi, I am trying to clock gate a very basic circuit using the power compiler. I have attached the vhd file of the design. When synthesize the design i give compile_ultra -gate_clock so that DC performs clock gating during synthesis. I report the Clock gating information using report_clock_gating command directed to a text file My design
I want to obtain power numbers from ptpx on an RTL based design. Gate level sims are not ready yet. Currently I have a RTL simulation pattern that I have converted to SAIF. This file is read into the synthesis flow to generate a SAIF_MAP file. I then read the SAIF_MAP and SAIF pattern files into ptpx to obtain an average power (...)
hi everyone, i am using Xilinx 9.1 synthesizer to synthesis my design. i used Xpower Analyser option to find out power but it gives me the same power for any RTL i use. What is the reason and how to rectify it. ?
by design you could define a "master" clock gating, and add local clock gsating (in RTL or by synthesis tool) to reduce the power consumption. The idea is to place the clock gate as closest as possible of the clock source, to have the maximum of buffers after this clock gate to reduce the clock tree consumption. Then one master clock gate close
Hi Can anybody please let me know the way to clculate power of a Gate level netlist using synthesis tool? Thanks
How to calculate the max current and typical current of a design while synthesizing the design? Is not it same as calulcating max power and typical power? How to ge that during synthesis in bothe the above cases. I know that report_power command in synthesis tool will report both the leakage and dynamic (...)
Hi All, I wonder if anyone would can share their FPGA reference flow or methodology scripts. Currently I'm looking at Altera's Quartus and would like to build a full design flow from compile (scripts going through different stages of synthesis, power checks, etc ) to finish. I think this should be already available somewhere and would help
Each instance of the the module can be implemented using different std.cells depends on timing/area/power requirments. So, one module can have different content after synthesis, but RTL had the same content. Uniquify makes copies for each instance of the module and make it possible to change module content independently.
yes, please check synthesis script before you do run!
some remarks: 1- large 40k? 2- how many scan clocks do you have? or do you ignore the jtag-flops from the scan? If you have only one scan clock domain, your design will synthesis fully synchronously, but your design requires to be simulate with two clock domains. 3- did you share the same power/ground lines between the analog and the digital par
There are three main constraints in ASIC synthesis Timing, Area and power. All these has trade-offs. If you wants better timing you may require large area and power. If you require small area your performance will effected.
hi folks, Iam trying my hand at power aware synthesis using synopsys upf flow. Here i will try to raise some doubts and share my experiences about this flow. Lets start with the most basic stuff create_power_domain command...iam unclear about importance of different scopes...can't we just remain at top scope and define all our (...)
Hi all, I'd like to ask you about the possibility of editing in the leakage current value of the cost function used in the power optimization algorithms in synthesis tools?Is it possible to do? and what is the recommended tool for that?:-D Thanks a lot Best, Hamzah.
Hi, If I understand it correct you designed a cache with multiple cache lines. Each cache line will be a set of register after synthesis. Now you want to put such a set of register into standby mode. In your design this would me, you need to disable the clock to this register. So you need to add a clock gate. In the end you will have for
Hi all, I have a problem with the synthesis of leon3... I want to have the post-synthesis verilog to make simulation with modelsim, have the VCD and the SAIF, to use primetime for power report... everything is ok but some module's names are too long and I can't write the DDC and primetime won't go... i tried to use change_names_rules (...)