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170 Threads found on edaboard.com: Synthesis Power
DC is a good tool for synthesis!
Critical path locates at a sub-block which occupies a seperate power domain. So I use hierarchical flow during synthesis. First, synthesize the sub-block with its own upf and write out subblock.ddc. Then during top synthesis, read top RTL and subblock.ddc, and propagate power supply data to top. After compile I cannot get (...)
dear all i have vhdl code for vga interface, i did all process such as synthesis and implementation so i need to know how i can use Xpower to measure all power ( power by Voltage Supplies,power by User Logic Resources,Thermal Powe) wait your reply regards
Dear, pls let me know how to optimize power in two stage op-amp ckt. with GP synthesis, in which sub-space max-monomial model of 0.18um used. This scheme is used to convert KVL constraint to a convex constraint without affecting the result.
Hi all, I've seen below thread: "thread23278" However, a couple of years passed since this thread has not been active. Every tool vendor is working hard to produce better tools, therefore I'm raising this question one more... For example we used powercentric of Azuro for our latest design and we've seen reduced power figures on clock tree...
the synthesis tool will choose for you the best flop for a path. if the path are less constraint, it could not choose the best one, but there isn't any impact on the design result. and Best means what? In power/timing/area domains?
Hi, In which stage we have to start CPF or UPF. RTL stage or synthesis stage or PNR stage. Regards, Ravi.
Hello I'm runnign synthesis with Design Compiler. After differents synthesis my results in report timing, says that the slack is zero or negative. So my question is, because i'm looking for positive slack for a secondary power optimization, how can I see the positive slack?
I tried to import Verilog netlist into schematics (I use Cadence virtuoso), and it asks for an "attribute file" (by default it should have the same file name as the netlist file with .attx extension). I don't know what that file is, and the synthesis process does not seem to produce the file. I heard it may be the information of power network, but
I am attempting to design a clock tree for a design with clock gating. I am having trouble understanding the syntax for the ctcsh. My design gates a clocks for power and functionality. In each case, devices clocked by the gated clock are expected to be synchronous with devices clocked by the ungated clock. Should I time through the enable/c
Hi, everybody. I am doing a low power design now, when doing synthesis using Design Compiler . There are many waring: The global net driven by pin *** is ineligible for level shifter insertion because some pins have directions other than in/out.(MV-613). Why this? Thanks for answering
hi all, if i give the set of libraries operating at diff voltages say 1.8,1.2, and a level shifter library, and use insert_level shifter cmd and then compile do the synthesis tool itself divides the power domains and insert level shifters to satisfy the constraints or should i nee d to explicitly assign the modules in my code to diff operating c
hi, i actually prepare my these in STericsson company, and my subject is low power technics in rtl synthesis and i am in aa step of documentation. I didn't understand the clock gating method, so i ask you to help me, also i hope you tell me if they are other methods of reducing power in digital design. even if you have documentations, (...)
after u are done with synthesis and P&R , follow these steps 1) Do RC extraction ( Parasitic extraction) . for eg. Synopsys Star-RC ( or Cadence Assura) Tool will do it. It will generate spef files. 2) Run STA for Timing Analysis for eg. Synopsys Primetime Tool will do it. Input to it is your spef file and gate-level netlist
Hi, I am comparing a number of arithmetic adders based on their power consumption. I use Synopsys Design Compiler for synthesis and Prime Time PX for power analysis (using back annotated SAIF files, from simulation in ModelSim). I can't figure out if the Synopsys tools are actually analyzing the power that is dissipated (...)
Hi all mentors, I am in urgent need of your help as I need to present my project to the professor. I have written a code and synthesized using xilinx and the details are { family: spartan3E Device: XC3S100E package: VQ100 speed: -5 synthesis Tool: XST(VHDL/Verilog) Simulator: Modelsim-XE Verilog Preferred Language: Verilog
Hi all, I am using the TSMC CMOS LOGIC 0.18um (3.3V) technology. I was wondering in which stage of the digital design flow would I have to mention about dual power supply (+/- 1.65 V). I am in the synthesis stage and the library I am using has a nominal voltage of 1.8 V for a tt process corner. There are no libraries with a nominal voltage of 3
The constant 1'b0 or 1'b1 in HDL is realized with a wire connecting to VDD or GND. That is fine until you consider the ESD issue where a gate of a MOS FET is connecting directly to the power supply or ground. That's where the tie on/off gates come in. They are usually provided by the standard cell library and synthesis tool can pick them up automat
Hi Chunwei, If you calculated the coefficients as amplitudes, you have to square them in order to have the power ratios needed for synthesis of splitters. Check your array synthesis method in order to be sure that the coefficients are in magnitude (and eventually phase as well) and not in power. Usually the (...)
power synthesis unsuccessful, can anyone tell me the possible problem?