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170 Threads found on Synthesis Power
Hi, A lot of the time I am conducting power estimation and I have a TCF file for a specific HLB in a design and would like to extract the average data activity and average clock activity so that I can make correlation study between power estimation from synthesis tool and RFI/RFQ stage power estimation. Is there a w
The ASIC synthesis tools like Cadence RTL Compiler will report static and dynamic power consumed in your design in the power reports. How does the tool calculate the dynamic power even without the switching information??
Hi All, while doing power estimation after synthesis. i am getting not-annotated nets. How can we exactly map the names? How to solve this annotation problem? The saif file is generated using Modelsim and synthesis file from design compiler. Please help. Regards
I synthesized Leon3 with two different options: flatten-all & auto-ungroup: [/LIST It produce a single top level verlig module with all the module merged inside. During synthesis there are some uninitialized FF which cause 'x' propagation and results in incomplete annotation while doing power estimation. For that I can in
Hello, i want to do a power analysis on the post-synthesis netlist of my design. My main design inputs are connected with one of my sub-designs inputs(i.e. with the component's A inputs). My main design outputs are connected with one of my sub-designs outputs(i.e. with the component's B inputs). Here is the problem: When i set constra
There are commands in upf to place switching fabric for power gating. Is it that this UPF can only be included during RTL synthesis and the netlist generated will have the switching fabric which cuts or supply the power whenever necessary? Is there any way to include low power things like switching fabric to be (...)
Hello All, I got really frustrated. I just need to synthesize very small design. But unfortunately I have just library with powered gates. I don't need sophisticated power management. I just need to have properly connected power nets. By normal synthesis I got design with floating power nets. I use (...)
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
If you have tight transition time during synthesis, may be fanout will be reduced.
Hi I want to know best synthesis tool for asic design. From web i have listed some like 1. Design Compiler by Synopsys 2. Encounter RTL Compiler by Cadence Design Systems 3. HDL Designer by Mentor Graphics 4. TalusDesign by Magma Design Automation I know it might be difficult to say best because it might depends on what to implemen
Hello, During a post synthesis power analysis I'm loading a parasitics file generated in DesignCompiler. I get following warning in PrimeTime : Warning: Reduced annotation reading must be enabled before reading a parasitics file which contains reduced annotations. (PARA-123) Can anyone please tell me how to enabl
Hi All, Do someone can tell more about the Multi power Domain Design (using UPF)? As far as I know, UPF is a TKL file, which define the power optimizations during synthesis. Correct? But how can it do it? Thank you!
Hi All, What reports should be generated after synthesis? What reports are most useful? Thank you!
Hello, I am estimating the power consumed by my circuit post-synthesis and also post-layout using PrimeTime. I am facing a strange problem regarding the estimated power. The procedure that I follow is: 1. Get VCD file form Modelsim. I use the command ?vcd add ?r /cpu_test/cpu_inst/*? and run for about sometime. 2. Run the script in (...)
Hi All, What should I check after logic synthesis? As for me, here is the list: 1) Timing Warnings (negative slacks) 2) Gate Count What am I missing? Thank you!
Then it should be the same as post synthesis netlist will be the same.
Hi guys, I had implemented clock gating using RTL similar to below. It works well during RTL simulation. However, after synthesis, I perform simulation on post-syn netlist with sdf back-annotation. Simulation show the system does not function correctly. assign cg__clk = clk || !clk_gate_en; my_module my_inst ( .clk_in(cg__clk), .....
Hi, I am new to APR so please excuse me if my questions seem lame. Should the netlist output from synthesis have VDD/VSS ? Also, Do I have to add power rings in Encounter to be able to place std cells ? As I do place but nothing appears in the layout . Thanks
I am not sure how useful primetime is... There's PrimeTime PX, which has power analysis. Design Compiler and RTL Compiler are commonly used for post-synthesis power analysis. - - - Updated - - - As for me, it's hard to understand how power Analys
You can use the report_power command in the synthesis script itself...