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Dear Friends,
I finished with the design of single ended OTA. the GBW was achieved is 20 MHz by driving capacitive load of 10 PF. Now I chnaged the design to fully differential OTA and I kept exactly the same biasing current or circuit transistor ratios, then I connected the smae load of 10 PF differentially between the two outputs to make a com
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-04-2019 17:26 :: Junus2012 :: Replies: 7 :: Views: 241
Hello guys,
I have implemented a PFD and Charge Pump and I wanted to do a simulation for them as part of a PLL.
without the need to perform verilogA components in cadence, I understood there is a way to take a complete PLL design in Simulink and replace some components with transistor level components from virtuoso.
here is a link that de
Software Problems, Hints and Reviews :: 12-04-2019 11:36 :: firasgany7 :: Replies: 0 :: Views: 162
Hello,
I need to calculate the CANH to CANL capacitance in following circuit.
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In the datasheet of the device the CAN input differential capacitance (Cdiff) is given as 10pF and additionally CANH and CANL (Ci) input capacitance is given as 20pF.
e.g
Analog Circuit Design :: 12-03-2019 08:15 :: ku637 :: Replies: 1 :: Views: 167
I made a helicail coil and have about 250 turns,
how can i made it to be natural resonance?
Electromagnetic Design and Simulation :: 12-03-2019 13:23 :: Addisfira :: Replies: 3 :: Views: 182
Some distros are much more helpful / forgiving than others.
Ubuntu worked out pretty well for me, on a Dell which has
a near-orphan GPU. Red Hat / CentOS, I could never get
the display right on.
Seems like the "easy" installs want to set you up with the
desktop / GUI interface on boot. That's not going to work
out well if you don't have (that
General Computer :: 12-03-2019 05:12 :: dick_freebird :: Replies: 6 :: Views: 1084
hey
I have a simple setup with P32MZ2048EFH144
It has no external oscillator.
I have a simple code with Delay_ms(1000) which appears to work fine (the led blinks at about 1 second)
But....
I think there is something I dont understand.
take a look:
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No matter what I set in "MCU Clock Frequency ", the blinki
Microcontrollers :: 11-29-2019 20:34 :: K33rg4t3 :: Replies: 3 :: Views: 339
For a project i'm doing, I am trying to keep the switch panel relatively compact and not running wires from the switch to the board. Utilizing switches such as the one linked below, what are some ways I could directly connect them to a pcb? I was thinking of adding PTH slots to directly solder the switches into. I would like a way to remove/switch
Hobby Circuits and Small Projects Problems :: 11-30-2019 00:04 :: Nabors :: Replies: 1 :: Views: 205
None of those regulators have any PSRR left at the fundamental
so I wouldn't rule out conducted emissions / susceptibility as
potential actors. Maybe a RF choke between regulators and
each of their "clients" is a worthwhile experiment.
I'd bet you could find 433MHz notch-pass filters from Mini-Circuits
or somebody. The problem could just be LNA sa
RF, Microwave, Antennas and Optics :: 11-29-2019 22:12 :: dick_freebird :: Replies: 6 :: Views: 368
Thank you Brian. Yes, I was referring to the domestic FM broadcast, but as I am planning to only demodulate the mono channel, I thought that I would only care about 15KHz bandwidth. I was considering to use the CD4046 or LM567 which both cannot work at 10.7MHz, hence was considering a second mixer to take the frequency down to this level where thes
RF, Microwave, Antennas and Optics :: 11-28-2019 11:27 :: aht2000 :: Replies: 7 :: Views: 348
I'm reading the following paper about SNAPBACK
--------------------------------------------------------------------------------------------------------
In the case of positive ESD stress, the VGBNPN
is triggered when the voltage on the collector electrode reach
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-25-2019 12:46 :: MubarakKhan :: Replies: 2 :: Views: 175
Dear friends,
I am designing the circuit shown in the figure below, In my first design I didn't use the source floower transistors MT1 and MT2, thus I gout a high current at the output stage (1.3mA). It was explaned by Allen holberg that the use of the source follower is to shift the dc level to the output stage so VSG6= VSD4, comparing without
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-05-2019 15:26 :: Junus2012 :: Replies: 5 :: Views: 387
Stariver Circuit is a factory of PCB based in Shenzhen. We mainly produce 2-12 layers PCB and applications are widely use in all kinds of area such as Medical ,industrial, Telecommunications, Consumer Products , Power supply, IOT etc. We covers the PCB production from prototyping to medium production to mass production. We can also supply services
Business, Promotions, Advertising :: 11-26-2019 09:32 :: Luciano_zhang :: Replies: 0 :: Views: 7
Hi,
I would suggest you check for continuity of the relay terminals to determine the NO, C and NC terminals of the relay. It seems to me like you have mistaken NC for NO.
Power Electronics :: 11-23-2019 18:44 :: Akanimo :: Replies: 25 :: Views: 878
Hi,
Sure you mean EMC?
Your description rather sounds like "ESD" or "Surge pulse" ....
EMC is high frequency. You may protect against EMC problems by using a low pass filter.
ESD is high voltage, with relatively low energy. You may protact against ESD problems by using a ESD protection diode.
Surge is not that high voltage as ESD but with muc
Analog Circuit Design :: 11-25-2019 09:07 :: KlausST :: Replies: 4 :: Views: 233
CORDIC is an algorithm for performing calculations. A LUT is simply that, a look-up table: phase in, amplitude out. The CORDIC implementation takes several cycles to produce an output; a LUT produces an output in a single cycle. I suspect MATLAB recommends a LUT based approach because it’s faster.
Microcontrollers :: 11-25-2019 00:36 :: barry :: Replies: 15 :: Views: 736
If you ran the same code at the same clock speed in all 3 FPGAs, it would take the same time in every FPGA.
They are not processors - they allow you to design hardware. And hardware will always take a fixed time to process, depending on how you design it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-24-2019 14:36 :: TrickyDicky :: Replies: 5 :: Views: 385
Hello guys,
i am currently working on my final project, and its about eddy current brake. But when i want to simulate the design, and of course i use set eddy effect, on the excitations, but when i use that message error appear, can someone help me with this? Thank you.
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Electromagnetic Design and Simulation :: 11-23-2019 09:11 :: sieghart15 :: Replies: 0 :: Views: 183
I am not exactly "expert" in this field, but I would try a few protoypes based on PCB design. The good starting point will be AN2866 application note from ST Microelectronics "How to design a 13.56 MHz customized antenna for ST25 NFC / RFID Tags" - it explaint theory and practiocal approach. When it will come to actual design of the coil, take a lo
RF, Microwave, Antennas and Optics :: 11-21-2019 15:29 :: alftel :: Replies: 2 :: Views: 504
Hi,
in the datasheet there is a chapter "Design considerations".
If you donīt keep on them you should not be surprised if it does not work.
--> your PCB layout is not suitable. It needs a solid GND plane.. and you need to take core of the other design informations.
Klaus
Power Electronics :: 11-20-2019 13:03 :: KlausST :: Replies: 17 :: Views: 791
gm=derivative(Ids/Vgs)(whilst Vds=constant)
Obtain Ids vs Vgs and take the derivative of this curve..
Analog Circuit Design :: 11-19-2019 08:06 :: BigBoss :: Replies: 7 :: Views: 398