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32 Threads found on edaboard.com: Technolgy
Hi I need SINEWAVE UPS technolgy, with code, sample board, etc. Any one interested to sell may contact me Microcon555
Hey people I am looking for a good selection of micro / tactile switch type keyboard / alphanumeric display controller chips to build a couple of general purpose I/O modules for all the PIC projects I seem to be doing lately. I found a PT6961 by 'Princeton technolgy Corp.' in an old VCR and built this, but it's a bit dodgy. Ele
Dear jimspring03. I have the same problem with the same technolgy (UMC 0.13um RFCMOS). All devices in schematic netlist (SUBCKT statements missing, exactly as in your attached file) are not find in the netlist. Did you find the solution? See attached screen. Best regards, André. - - - Updated - - - My scree
Hi, Check your technolgy libraries, it is usually already have there. If not, then you can make spiral inductor with VPCM.
What should be power supply value, gm and also of the WIDTH for 22nm technology????
hello, i am simulating a RLC circuit with a diode in it in cadence UMC_180nm technolgy.But a error is coming that include the diode model first..Actually i had taken the diode from what i can do to make this circuit working??? thank you
Hi all , I want to know the Advantages of 135nm technology over 180nm technolgy. why we are merging from higher nm to lower nm??????????
Can anyone help me to the working of "dailing " to an isp for gprs connection establishment ? I mean the working principle behind it ? that is dailing to a number and authentication occuring etc ? what are the devices using for this purpose ?please explain with example
Stuck at test is done at lower frequencies(10-50 MHz). It detects stuck at faults means a particular line is stuck to ground or VDD and opens and shorts in circuits. Transition test is done at speed (actual operating frequency of design). It detect transtion vilations. In lower technolgy node nets are sitting very close. This can lead to crosstalk
hello members i am very confused with that technolgy ,i know little bit and have idea ,but get mesh with cc2500 and xibee ,rf 434 mhz and rfid function generator,ir 30 khz generator,and electro magnetic 10 mhz and wireless door bell technology based at simple circuit. so in these there is difference but when to choose acording to my applicatio
Hi... What is the difference between TSMC 2P4M 0.35um technology and only TSMC 0.35um technology. I have model file of TSMC 0.35um, I need to simulate my circuit using TSMC 2P4M 0.35um technology. are Model files of TSMC 0.35um and TSMC 2P4M 0.35um different ?? Thanks....
do u have any idea about any low voltage(5v) devices which can give a mechanical output when voltage is applied(like solenoid):smile:
Hello, everyone. Through a personal contact I came across a job offer posting from Accelogic, a Ft. Lauderdale based high technolgy company, on which like they are looking for a high caliber and super-brilliant Senior FPGA Engineer to join them in an exciting position on which the successful candidate will have chances to leverage all of his/her
USB uses low voltage differential signalling and the transceivers have been developed and tuned for higher speeds. RS485 also uses differential signalling, but is considered an older technolgy, so I doubt if much work goes into improving the speeds. USB 3 is on the way with speeds of up to 4.8 Gbit/s (600 MB/s).
what are the techniques we have to use while doing PLL layout, especially VCO. why it is difficult. now which technolgy is using for PLL (mean 90nm or 130nm or 180nm). one more question , why charge pump is so difficult than VCO. can anybody tell about CCO , in which case we will use VCO and in which case CCO. can anybody answ
it is digital phase locked loop paper on 90 nm technolgy
Hi frds, i am designing a telescopic ota for 1V diff peak-peak swing i am using 1.8v supply with 0.18u technolgy. but i am unable to get the required swing, i am getting it around 0.7v only how can i increase the swing.
CMOS process technologies are available from most foundries in these gate lengths : 0.18 ?m, 0.13 ?m, 90 nm, 65 nm, 45 nm etc. What factor determines the scaling from one technolgy to another ? One trend i notice is that there is divide by 2 scaling in every alternate generations , ie, 0.18 /2 is 90 nm, 90nm/2 = 45nm, 0.13/2 is 65 nm etc..
What is technolgy file & how it is used in Virtuoso?..
CMOS, better state which technolgy. We use CMOS 0.35 0.18 It's not precise just state CMOS