420 Threads found on edaboard.com: Template
You can set all the defaults from pull-down "Options" -> "Design template"
The title blocks are in \tools\capture\library\CAPSYM.OLB
Open the library to see the "stock" title blocks. Use as-is or copy and modify your own
PCB Routing Schematic Layout software and Simulation :: 03-24-2017 11:23 :: spudboy488 :: Replies: 1 :: Views: 532
I want to scan finger library of R305 module.5 finger images are already enrolled in that module.I want to write code for scanning and displaying whether "found" or "not found"
So,once i collect finger image,what operation i need to perform?,whether i need to make template/character file or need not make it?
Microcontrollers :: 03-08-2017 10:59 :: akshaybhavsar :: Replies: 0 :: Views: 493
Congratulations on compiling such a paper -- it's a bit of work, and you've obviously put alot of thought and effort into it.
Actually, he didn't wrote the paper, he used it as design template.
How did you simulated your antenna and what software are you using?
Electromagnetic Design and Simulation :: 02-28-2017 16:47 :: johnjoe :: Replies: 4 :: Views: 366
on the other hand, you can add your own parameter name and put "=YourOwn" in template file (schdot)
PCB Routing Schematic Layout software and Simulation :: 02-24-2017 14:43 :: BuBEE :: Replies: 2 :: Views: 585
There are few or no ready-to-use C code examples on the Web about implementation of (secure) file transfer protocols with the ESP8266 (ftp, ssh, etc ...) working as client. Most of them cover the HTTP so that based on these source-codes as a template for your project, you would certainly send this via POST command, but on the file server-side you s
IoT - Internet of Things :: 01-12-2017 17:20 :: andre_teprom :: Replies: 1 :: Views: 3258
Here is a forum proposed to host technical discussions; I do not feel encouraged to help someone who can take a degree without even trying to start a single line of code. There are a lot of examples on Edaboard with which you could start as template. If you have some knowledge in programming you'll see that it is possible to do that.
Microcontrollers :: 01-10-2017 14:45 :: andre_teprom :: Replies: 3 :: Views: 556
The same diodes + voltage divider level shift circuit can be found in many controller ICs with internal error amplifier. May be they just copied a design template. I don't see the purpose of asking "what's the purpose of".
Just take it as is. The specified characteristic is achieved with this circuit in place.
Power Electronics :: 12-28-2016 12:29 :: FvM :: Replies: 12 :: Views: 599
If you are doing negative numbers, why are you using unsigned type?
Also, why are you using all asynchronous logic constructs? why no synchronous logic, or at least, why are you not using the template? your synchronous logic descriptions will not currently synthesise, as you are creating a latch, not a register, and you're going to create a logic l
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-07-2016 12:37 :: TrickyDicky :: Replies: 12 :: Views: 711
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Business, Promotions, Advertising :: 11-27-2016 06:37 :: Paullu :: Replies: 0 :: Views: 4
I am facing problem in finding the input impedance of a unit cell FSS in CST with FSS unit cell template. BY applying unit cell boundary conditions and floquet ports and then simulating with frequency domain solver, I get the S parameters but the input impedance is not calculated. BY simulating simultaneously with floquet ports and waveguide
RF, Microwave, Antennas and Optics :: 11-26-2016 10:52 :: engr.hamza :: Replies: 0 :: Views: 797
Quartus synthesizes the miso output register code because it can be rewritten as regular synchronous register description according to the template. Just pull-out rising_edge(clk).
There are however many latches generated and missing sensitivity list entries will probably cause simulation to synthesis mismatch.
Don't know why the design is wr
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-22-2016 13:59 :: FvM :: Replies: 4 :: Views: 1731
I am trying to simulate a unit cell by eigenmode solver in CST 2014. I use steps as: "Eigenmode solver -> Parameter Sweep -> Results template -> 2D, 3D Field results -> 3D eigenmode result". I obtained the plot of "frequency vs phase". My question is: How can i obtain the final dispersion diagram (frequency vs beta)
Electromagnetic Design and Simulation :: 11-17-2016 00:18 :: blackouttt :: Replies: 0 :: Views: 916
Use the conventional equation y=const* (x^2) and plot out the curves manually. Use different values for the const to get different shapes. Then make a template and use that ...
Electromagnetic Design and Simulation :: 11-14-2016 03:08 :: c_mitra :: Replies: 1 :: Views: 758
Use assignment editor rather than pin planner, or check the .qsf file to see if there is another variable handling these pins. You are perhaps using as template a design not 'empty', so something is likely already assigned to those pins as they said above.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-10-2016 10:31 :: andre_teprom :: Replies: 11 :: Views: 1414
You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation.
Yes, you can do that. But I presume the thread topic is learning valid VHDL syntax rather than using a non-portable method to
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-04-2016 17:07 :: FvM :: Replies: 6 :: Views: 780
A better solution!? How about using the STANDARD template for a resetable FF. Maybe you should go find the Altera and Xilinx documents on writing synthesizable code.
@lh- , Hear what they are telling you; the the right thing to do is to take advantage of templates provided by FPGA manufacturers, which have either th
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-03-2016 15:28 :: andre_teprom :: Replies: 8 :: Views: 636
You spent an excessive amount of lines of code just to initialize unused (at least not yet) resources of the core and their respective comments, whereas most elementary assignments are not present in your code, such as TRISB for example. You should consider using a simplest template to start a simple task as you want to do.
Microcontrollers :: 11-01-2016 22:04 :: andre_teprom :: Replies: 3 :: Views: 499
I am new to ADS and looking to simulate a RF power detector with a Schottky diode. I have created the diode model (see attached below) with all parasitic elements, but am struggling to simulate the whole circuit. Which solver/template should I use to do so ?
Ideally, I'd like to get a Vout vs. RFpower plot and the time response (Vout vs
RF, Microwave, Antennas and Optics :: 10-24-2016 15:45 :: Dirtyfighter :: Replies: 1 :: Views: 1290
As a concept, it is odd to intentionally create an async reset that is actually a sync reset.
The Verilog always construct describes an asynchronous reset. You might say that it's odd in some way that an asynchronous input is described by a negedge event. The synthesis template for a edge triggered register with asynchronous
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-14-2016 09:55 :: FvM :: Replies: 5 :: Views: 651
I'm not expert on FPGA fields, but every time I see someone requesting a peculiar control system that could be typically implemented on uCs ( I mean, no strict requirement to do it in hard logic ) I feel the lack of prior knowledge background on both subjects, or at least no previous effort to start from template/scratch. I would recommend you give
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-05-2016 11:26 :: andre_teprom :: Replies: 3 :: Views: 726