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I am working of quartus tool. should anybody tell me how to read and write on memory of stratix v fpga? how to make test bench for it? i just want to read and write on chip memory (ram) in mlab of stratix v.
Example design gives you test bench also where u can simulate and see the result... By using MIG u can generate core for specific need to convert one device code to another one..
hi, i am trying to use the MegaWizard tool for floating point division from Quartus, but when i run the test bench for the design i keep getting this error message Fatal error in Process memory at C:/altera/12.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39809 # HDL call (...)
Hi Dave, Wont it be better to use this for-loop in test-bench and load the calculated values into RTL during reset? AM nt sure. Pl guide.
I'm not using Xilinx and don't know if it's supporting the way you are reading the text file into a temporary array. In any case it's an unnecessary long winded method. Most people would simply read the text in the test bench top level. open text file for each line read text write array data close text file
To read array from test bench use: initial $readmemh("data.txt",mem); In above case you read hex data from data.txt file to read memory data. You can use for loop to traverse through all the location. To write data to text file use: $dumpfile("data.txt"); Hope this helps
Large Look Up Tables are really ROM memories. You can instantiate a memory in verilog and then give each memory location an initial condition in the test bench. I have also loaded these testbench memories from an external file in the test bench. In real (...)