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148 Threads found on Test Compiler
hello, i tried also to manage a 128x64 GLCD .. PIC 18F26K22 , test Afficheur Digitron SG12864-J5 but blocked with grafic functions i only can display texte ... it seem very complicated compare to a nokia 5110 with lower resolution 96x48 maybe it can
Dear all, I need to feed a sample circuit with a number of random inputs (say for example 1000 input patterns) and then obtain a power trace (power consumed by the circuit during applying the input patterns). As the test circuit may not be small or the number of input patterns may be high, i don't want to use Hspice as it may take a long time. S
use a "set_dont_touch" to do what you are asking. Now explain why DC's answer won't work for your design. The usual answer is that DC's logic can create glitch hazards and you need that node to be glitch free so you hand craft your own de-glitched logic solution. That's good. Now how are you going to test your logic? Scan test doesn't work on g
Hello, this is my first Project with microchip microcontrollers. I have to develop a emulated eeprom over embedded flash, and I am using the microchip aplication note AN1095, but it does not work properly. This is developed for C30 compiler, and I have to use XC16. I have been able to compile and execute the code, but when I test the EEPROM,
Hi all, I am working on a DFT . its an academic project where iam using cadence tools - genus synthesis solution (formerly RTL compiler) for DFT and Encounter test(ET) for ATPG. now the question is, after performing DFT synthesis, i was supposed to write ET scripts which were used by ET for generating testpatterns with the command : (...)
Hi guys, I am using clock gating in cadence RTL compiler, but there is no ICG cell in the library. So I implemented an ICG cell with code, which is active high ICG cell module ICG_posedge( input ck_in, input enable, input test, output ck_out ); reg en1; wire tm_out, ck_inb; assign tm_out = enable | test ; assign
Hi, I am using RTL compiler for synthsise, and I want to implement clock gating. I don't have ICG cell, so I wrote a module as the clock-gating module, which has "ck, D,Q,enable, test", where test is the clock gating control signal. module ICG_posedge ( input ck_in, enable ,test, output ck_out ); reg en1; (...)
Dear All, I have a .v file and i have done scan synthesis using RTL compiler. Now how to approach for doing ATPG using the ENCOUNTER test(ET)? Do I need to export the scan.def file to ET for doing atpg/ fault analysis? I don't know the exact command to do this export thing. Kindly Help ASAP.
Hi, I have cadence Encounter test 14.20 and RTL compiler 14.24. I want to do MBIST using this licences. Is it going to affect the flow with respect to Encounter 15.20 and RTL compiler 14.24?
Hi, I have a design in which there is compiler directive named "BFM". It is defined in one of the include files as `define BFM and by default is enabled. The purpose of this `define is to make a connection to a certain module in my top-level test-bench and is meant to be used only during simulation for a certain test. Consequently (...)
Hello I am new with PIC 16f676 . How do i test a simple program and run it using PIC16f676. Which software do i need to install and test it ? Also how do i compile and run it ? Thank you
I'm assuming DFT means design for test? What type of DRC errors are you getting? I tend to ignore ones about incomplete tristate buffers if my DFT is just outputting internal signals. I pay more attention to clock crossing. It's more like a set of guidelines. Wes
Hi, i dont have mplab at the moment to test the code. have you tried to simulate it in mplab? check if the trigger works properly, and also on different frequencies.
I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler. I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib). In the work folder i type these commands : 1)rc (...)
i write a code to test my HC-SR04 sensor to measure distance but seem there is no responce from the sensor, after i program and when i turn on the pic, the LED from port A0 turn on and not turn off even i move more than 100 cm..pls help i'm using pickit 2, mplab ide wit c18 compiler, internal OSC 4Mhz.. tq #include #includ
Aaaaalways test your communications with a known host.. like communicating each board with a PC first... (go buy a cheap usb/ttl cable to test ) then, what compiler are you using? It seems XC8 but... finally... did you read the XC8 Peripheral Library Manual? it seems you need to use the OR operator '|' to join the settings Open2USART
Hello, i have some problem with my design. when a make the syntesis with design compiler, i get the error : The tool has just encountered a fatal error: If you encountered this fatal error when using the most recent Synopsys release, submit this stack trace and a test case that reproduces the problem to the Synopsys Support Center by using
If Proteus doesn't have the model for PIC16F72 then use the compiler's debugger to test.
Sir , I used Cadence RTL compiler to generate the netlist.Then tried to do netlist simulation in NCLAUNCH files used netlist.v (netlist generated by rc) and test bench When I compiled there was no error but upon elaborating test bench am getting this error but am getting this error ncelab: *E,CUVMUR (...)
Please zip and post your PIC18 Simulator IDE basic or assembler program file. I will test it. maybe you are using demo version of PIC18 Simulator IDE which doesn't support math operations. In basic + is used for addition and also string concatanation. It seems + is working as concatanation operator.