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42 Threads found on edaboard.com: Test Plan
Has anyone ever tried this schematic done by Swagatam I like his circuits I have some of the parts of the circuit I plan to build the high frequency section of it I think the only thing I wouldnt have is the 20uf caps at the input I plan to just use 24v to test it, Can I use 2 10 uf 400v caps at the input thats all I have now after a while I (...)
Hi, I want to test an LNA IC. I want to use supply of 0.7V and make it as low noise as possible. I plan to use a 6V lead acid battery and then use a voltage regulator as follows Can anybody suggest better ways? The lab power supplies that I have make the noise figure 1dB worse.
Dear Board i ve Canalyzer with me and i know basic CAPL scripting. with CAPL i can do some test cases successfully for easy working. But i need to implement image processing but i dont know how to do it with CAPL. so, i plan to take canalyzer COM server to VB6.0 and send some message from there to vector canalyzer (in physical vehicle network)
Hi, I already design a LNA schematic and layout, so far so good. Now, I plan to make it as a differential pair LNA... I had some idea about the schematic and test bench, but it does not work very good specially when it comes to layout. Can anybody introduce me the references I can use for finding the structure os schematic and also the (...)
I have taped out a chip for low power ECG acquisition. I have to plan to test the chip when it comes back. Regarding the same, I would like to have some information about the test set-up used for the testing if the chip. What are the instruments used for the testing -company and instrument number, (...)
I've not used Altera SERDES, but designed many SERDES in the 70's (DS1 BER test sets etc) 1) Normally bit clock VCO runs at 2f with quadrature 1f outputs, quadrature (90deg) 1clocks should be available. Pre-Comp, may help improve SNR or jitter reduction, but watch out for ISI and group delay distortion. plan on doing BER margin
Hello, I am in the phase of designing and implementing a digital circuit for a FPGA.I wonder how a digital circuit logic(described in HDL) is verified before synthesizing to a FPGA.I used to write test bench for simple digital circuit before but the design at hand is now complex and writing test bench doesn't look like a wise approach.I have
Hello, I would like to plan a test PCB with multiple components that will interface to automatic tester with PCI edge connector. Since I would like to conduct test of up to 300VDC, I want to know what is the maximum voltage allowed between 2 adjacent PCI edge connector on PCB? How is it dependent on temperature? (...)
hi guys i wrote a big program for an electronic system based on pic microcontroller after testing i didnt find any problem but im going to design a test plan to will sure system hasnt problem how must be design an embedded software test plan. please help:roll::roll: Hi, I have some experience of this. (...)
Hi All, I need some advice if possible on how to make the first investigations on a system for noise cancellation/ noise removal. My plan is to place a speaker and a microphone (standard speaker/mike, low cost, non callibrated type) in a room, connect it to a PC audiocard and test if it can attenuate the sound level in the room, being speach
What battery/battery bank capacity you plan to use with this 600W or 1000W inverter ? What working time and battery/battery bank life you expect ? In bottom right corner of circuit diagram, you have author email address. Its best to hear him, because he try and test device. Best regards, Peter
My input signal is a multi-channel/carrier OFDM. Each channel have 5MHz bandwitdh. Now, I would like to simulate a 2-tone test for its IMD. I plan to measure the 3rd order at say +/-0.2 MHz offsets from the edge (4.8MHz and 5.2MHz). My computation is a spacing of Fcarrier +/-1.8GHz, in order to create the 3rd order tones. Is this correct?
Hi i have one interview question.....? how you verify your mod10counter.....? how u write test cases and verification plan for u r mod10 counter.....? i need exact answer for this.......?
There are EMC standards for ingress that a designer needs to be aware of for interference. THese exist in Europe (CE) USA (FCC) and Japan as well as other nations. We used to test for ingress with AC lines and brush type electric motors with data cables next to it for measuring coupling. So I would plan on designing a shield from ingress. THis can
how to make test plan for asynchronous fifo which have write clock =250 Mhz and read =125Mhz specification: wr , wr_clk, rd, rd_signal, data bit 8bits, deapth of FIFO 16 bit
oh, that some basic stuff: 1- write spec/verification plan 2- write RTL & TB 3- write tests (simulation) 4- this code could test ON FPGA or CPLD (two differents technologies, depend of your goal) 5- synthesis/DFT to your technology target 6- place/CTS/hold/Route 7- STA 8- along 5-6-7, LEC & ATPG 1 to 3 is mainly the frontend 5 to (...)
test plan : It is your plan to test the DUT(Design Under test). That is, all the necessary tests to be done on the DUT to check all the features. test Bench : It is module to give the stimulus (input) to the DUT. In this you will drive the values as per your requirement. (...)
I was asked "How to verify a 16 bit adder and a 256 bit counter." I was asked how I will develop a test plan to effectively test the above circuits. They dont want the exhaustive testing of the circuit. Please share your answers. Many Thanks!
Could anyone suggest proper arrangement for construction of barrier arm Any mechanical dimension construction we need We have made test setup Before without attachment of the arm we are found out that gear box and arm attachment rod is well working according to plan. But when we attach the arm then the rod attachment with arm is not stable as