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HI, I am trying to configure Altera TSE MAc using Avalon MM interface (without using SOPC). I am trying to write the scratch register (address 8'h01) with 32'haaaaaaaa but not successful as waitrequest signal is high throughout simulation... I am providing 50 MHz clk for Avalon-MM interface and 125MHz clk for ff_tx_clk, ff_rx_clk, tx_clk,
hello! can anyone help me step by step to design an LNA on 130nm IBM on cadence?I am designing for WLAn 11g at 2.4 GHZ and bandwidth is 167MHz.I have reached a cascode stage but getting warning like vgs-vbs is -2.74 exceeds lower limit -2.6.Can somebody suggest the reason of this warning and keep hepling throughout my design?
Hi, throughout the elementry electronics text we come across the term current source. I have never seen a current source in real can anybody elaborate what actually a current source is and what sources in real life can be regarded as current source...Whats the physical significance of current source and how it is different from voltag
Does anyone know what serial communication protocols are used in Scion cars? I know they use CAN but I don't think it's used throughout the car's electronics. I captured this stream of serial data and I'm trying to determine the protocol. The baud rate is 2.4k. I don't think it's CAN because the baud rate is too low. I thought that the prot
I had posted the same thing on another thread... but it seems this is the right place to ask such a question... I want to make a small model (prototype) of a whole telephone exchange structure. with 2 subscribers on each side and in between them 2 exchanges too. plus an optional addition of more subscribers anywhere throughout the line. I will
Hello there.. Long time no see... I want to make a small model (prototype) of a whole telephone exchange structure. with 2 subscribers on each side and in between them 2 exchanges too. plus an optional addition of more subscribers anywhere throughout the line. I will need a hybrid transformer. and what all will I need. plz guide me as t how to g
CAN only defines a low level protocol. What you are asking is defined in higher level protocols such as J1939 for heavy trucks. Information about CAN and the underlying protocol can be found in many places throughout the WWW and this is one you could start with You might want to take the class CAN bus
hi,good day to everyone... I have a hard time throughout the process of learning serial communication, but gained nothing at last. I tried with 2 PIC where each of the PIC will control the LED that connected with it. There are 2 PIC in the drawing. Let the left PIC = A, right PIC = B. What i want to have is....A control the LED that connected
hi yes i agree with Abhishekabs. for xy plane pattern you need to fix theta=90 and vary the phi angle throughout the 360 degrees. i hope it works regards
Double Sided PCBs (quick turn up 48 hrs) Multi-layers PCBs (up to 30 layers) Flexible PCBs and Rigid-Flexible boards (1-6 layers) Aluminum base board and other metal core board We already work with several international companies throughout the electronics world although this doesn't mean that we are only interested in large orders.
Hi Friends, I want to measure a linear displacement between two blades through that I can set the gap b/w them. Sensor range is 0-25mm and accuracy should be less than .01.I was searching for the sensor throughout the day. But I am not sure which one I can select for this. Please help me to find a suitable sensor for this application. Thank
instead of having wires/contacts taken out of the corners or periphery of a chip, its possible to place the contacts throughout the chip using a method called flipchip. compared to other methods of packaging, flipchip provides a very cost effective solution. so it is preferred. u can take a look at this website to get a basic idea of flipchip.
You need these devices for synchronization purposes basically. There can only be so much clock skew throughout the chip. The highly the clock frequency the higher the chip performance but also there is higher power consumption and a more complex clock network.
This Xilinx info may help you. "Area Reduction Strategies": Also search the ISE "Synthesis and Simulation Design Guide" for the words "area" and "optimization". Various tips are scattered throughout that manual.
I assume you are using a divide-by-100-million counter to generate the 1 Hz signal. Feed that signal through a global clock buffer such as a BUFG. That should provide a nice low-skew clock throughout the FPGA.
Q will be tied to either 1 or 0 throughout, good solution
i've read that white gaussian noise has zero mean and a variance of 1. at the same time, the power spectral density has to be uniform all throughout in frequency. i am confused as to how to program in mathcad to generate this noise and i need some clarification to fully understand this. thanks for the help in advance.
If you are talking about clock fanout inside the FPGA, you can buffer the counter output with a BUFG primitive, or one of its relatives (see your ISE Libraries Guide). That global clock buffer drives a low-skew clock net throughout the FPGA.
does anyone have any idea obout this type of antenna or anywhere can i find the information about it i've search throughout the google but many are not related to what i want regards, niena
Heres the deal. I am using the nVidia Geforce 6800 Ultra to perform calculations. However, I need to output this data to an external device (at 580Gbits/s). I plan on distributing the data throughout multiple devices, so I am trying to determine the method with the best bandwidth. Here are my approaches: 1) I originally