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Rather than hi-jacking the thread "Precision op amps - is 1 microvolt offset believable?", I decided to open a new topic. After reading the thread above, I remembered that I had an OPA735 (bought brand new from Digikey) and decided to play with it a little. You know, I had nothing better to do on a dreary Sunday afternoon. I built a classic d
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NMOS and PMOS are your explicit, desired devices. Each has parasitic BJT "baggage". Thie baggage forms numerous SCR structures throughout the chip and each one needs to have a wide enough base and a stiff enough base- emitter shunt, that SCR triggering won't happen and holding will quench. NMOS forms lateral NPNs to NWell and other NMOS. PMOS in
If you?ve had your share of indefinitely delayed projects working with cheap outsourcing ?sweatshops? that end up costing you more in the long run, then you can appreciate the importance of having the right tech partner by your side that is dedicated to making your product a reality. High-tech engineering requires a combination of skilled
Thanks for your replies. I guess what it comes down to is that it's quite hard to calculate switching losses as they depend on a lot of factors, and that the calculations from my first post are about twice as high as a typical worst case scenario because they assume max voltage and current throughout the whole switching process instead of a
Hi, as you can see in the attached picture, i have a setup of two antennas interacting throughout a mirror (blue arrows). to avoid crosstalk (red arrow) of the antennas, a absorber is placed. To model this in an HFSS Design, i used for the antennas a volume with Finite Element Boundary Integral (FE-BI). For the metallic mirror i use a Hybrid Reg
The simple mention of 4-20mA sensors suggests the action of remote measurement, which by itself would be a strong argument for using galvanic isolation, such as analogue optical couplers. Unfortunately many questions here are posed not contextualized, and probably only throughout the replies is that needed information will arise, by increments.
I like to fill with decoupling capacitors, which I make by stacking metal layers over (say) 20/5 multifinger MOSFETs for a parallel thin ox, thick ox plate set. This can be positive for density checks and gives some improvement in chip behavior (killing supply bondwire inductance somewhat). I sometimes make this all part of the power supply bussin
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Hi, I have the lead-free solder in 1.pdf (Sn/Cu). At 2.pdf a typical SAC305 alloy is shown. I see many impurities and in the case of my solder (Sn/Cu) there are more metals in it. Should I worry about poisoning myself (primarily through skin contact or possible inhalation of any vaporized micro-metal particles) throughout the years of soldering w
Hello, using Verilog and I am creating a 'memory', e.g.: reg registers ; This memory is read/write accessible via a bus, and some of the bits will be read only and some will be write only. I am trying to construct a "core-wide" set of definitions to use throughout my core so I can easily change the memory descriptio
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Class II devices are throughout protected by double or reinforced insulation and don't involve a protective earth connection. Class I devices may expose circuits that are not connected to protective earth and thus need double or reinforced insulation. Examples are e.g. given in IEC 1010, Annex D.
Hello everyone, I have encountered this rather strange behaviour when writing .sdf files ( and simulating the corresponding netlist ). After placement step, the sdf file contains the following delays for a given path ( a flip flop ) : 1) clock pin to flip flop's clock input : 6ps delay ( interconnect delay ) 2) flip flop's clock to Q delay
1. Yes, but why do you need to convert width? why cant you just process the data in a pipeline? Width conversion is usually done because: - You are changing clock domains and need to maintain a specific throughout (from fast to slow clock) - You are limited by the interface required Otherwise its usually just easiest to use the width thats availa
moving average typically refers to the FIR filter where the previous N samples are added together and then the result is multiplied by 1/N. This filter is common because a recursive implementation requires very little resources. It should not be hard to find examples of this filter throughout the internet. Getting samples to the filter is up
A cryptographic-based standard solution may be too heavy depending on which microcontroller you are using. In other side, a solution based on a cypher with an unchanged key can be easily broken. Recently I have made an IoT-based project on which the solution that seemed more safe it was by encoding data with a key that was oftentimes changing depen
Look at the 'strtok' function. It is for searching for characters throughout a string and dividing it at that point (Tokenizing). If you loop the function until it returns nul (meaning it has reached the end of the string) and use '=' as the search character it will return a pointer to each of the values in turn, no matter how long the string is.
Hi all, I have designed a clock regeneration circuit for my Master thesis. Now I am in a need of designing a voltage offset compensation circuit for my entire circuit design. I have an emitter follower at the beginning of my clock regeration circuit design, so I thought emiiter follower is a voltage follower circuit and so, an offset compensati
Hi guys, Hope you can help me. I am testing a project fabricated in 130nm technology, with a supply voltage of 1V (Agilent E3631A) and a bypass capacitor of 100nF on a PCB. I connected Vdd first then gnd when the power supply was off, then turned the supply on and everything connected to gnd seems to be dead. I have a few biasing stages, just n