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73 Threads found on edaboard.com: Trace File
Hi guys. I am simulating a CPW with an extra SiO2 layer. The 2 wave ports are set to touch the two opposite surfaces of the trace. I first looked my s11 parameter, it's below -20dB, which seems all right. However, when I checked the z11 plot and found the real part is not 50ohms while the imaginary part is quite large. This is really confusing
Code debugging is the way to go. Check if all temperature sensors are responding at all (e.g. do ACK) and if they are sending the expected data on the I2C byte level. Then trace the further data processing. Although not very convenient, you can do some source level debugging in Proteus when loading the *.cof instead of the *.hex file. Are yo
trace code execution in simulator (preferably MPLAB SIM not Proteus), find out how you came to "some location".
In what sense? Modelsim will store the whole waveform file for you during a simulation run. If you're trying to store a trace to a text file for stimulus later, you will need to do that in your VHDL code.
Hi , I was trying to run Smoke analysis for the rfamp sample circuit. But when I run the transient simulation, PSPICE netlist shows some warnings like ?PSPICE template is not available? (Attached the snapshot ? rfamp_netlist warnings). Also transient simulation captures only the input signals V(in) and abs(V(in)) and I couldn?t even probe th
Dear friends please tell me how to import DSN file in diptrace
Can anyone please explain what a clock tree trace file is and the use of it?
I'm trying to extract a tree of instances of my systemverilog classes used in a testbench, but apparently there is no way to do that using DVE. When running a simulation interactively using DVE, it will generate a nice instance tree with instance name, class type, etc., and you can trace to see which class instantiated it. I'd like to be able to ex
... XC8 works fine in MPLAB. It's a stand alone compiler, the IDE you use (if any) isn't important. The OP wants to debug assembly language code. The best tool by far is MPLAB/MPLABX in which you can import your assembly instructions or a ready built .hex file and use the simulator to trace and monitor your program, register contents and variable
Hi, There is one line below the code dec 5 100 10MEG op=no I do not know what meaning of 'dec' is, where is it defined? Could you point me to a link/tutorial on the basics? Thanks, * .PRINTALL directive means: save all voltages and currents .PRINTALL * .trace directive define the simulation
Hi All, I am experiencing this weird problem. My encounter exits out after the PlaceDesign Step and gives a stack trace to file message. I have tried using encounter -64 -simplefont But not helpful, I still get the same problem. Really need help on this one. Since, I see no error and it just exits out. Here's what I get in my log (...)
"Grey" designates unknown state, e.g. floating input. If it's observed with pins that should be initialized as outputs, it means that the code isn't executed regulary. To see why, you can load a *.cof instead of *.hex file and trace program execution in Proteus source level debugger. Although I won't contradict the Proteus qualification by Easyr
Who knows? trace the source of the common procedure file and inquire from Fastscan. In LOC test patterns, scan enable signal does not need to operate at system speed. Once scan data is loaded through scan chains, scan enable signal transitions to 0. Subsequently, launch and capture clock are applied. Launch vector should be calculated from the re
Hello all, I have made a PCB with soldermask clearance as 0(Dimensions-> Pads Mask Clearance-> 0) , but the fabrication people has sent it back saying "We found soldermask expose on trace on both circuit layer" . Why does this happen? Ive attached snippets of my PCB where the Fab ppl points out this problem. Thanks.
ya, you can do the single side board in allegro also,for single side board you need to route the trace in bottom layer.
hehe the whole idea behind gerber is that you cannot trace back the component name and pcb file it is a manufacturing file containing nothing but captions (pictures) of the PCB layers . so you can view the gerber file , use it , duplicate it , but no modification or altering can be made , understand the point buddy ?? It is (...)
trace your errors. Warning D:\karthick office work\projects\embedded\ONLINE MONITORING OF GEOLOGICAL CO2 STORAGE AND\1.code\full code\lcdportd.h; 5.1 function declared implicit int In your lcdportd header file, there is a function on line 5 that is declared as an implicit int. I assume this is your main file, you would n
How to automatically remove or detect open traces in the PCB design? Open trace i mean is a unwanted trace on the PCB.
Never seen a buffer added to clock on any DDR2 layout, all signals have some from an FPGA, Northbridge processor directly so cant comment. If the buffer is a true zero delay(! HOW) then both trace lengths have to be catered for.
Hi, I am getting stack trace error while using the synplify tool. Can anyone tell me what might be the exact reason behind it? Rgrds, Pravij


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