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Transistor Sizing Logic

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4 Threads found on Transistor Sizing Logic
9927199272 friends..i'ma beginner to cadence.. last day i tried to implement pose edge d flip flop using transistors(logic gates). Now i'm facing a problem.The circuit is passing data line on both edge of the clock. Can anybody help me to figure out what went wrong with this circuit design
please anybody tell me... Is it required transistor sizing when phase detector designing...iam not getting output at the PFD(iam using 0.18um cadence)...
I am just learning about electronics and i understand how transistors work but I am having trouble with the math side of things. I am studying the single transistor inverter (which I have drawn very poorly below). If i have a datasheet for the transistor i wish to use, what information do i need, and how do i use it, to work out what (...)
Hi friends, I want to learn how to size my inverter (or a nand gate) for a fan out of 4. i.e my gate has to drive 4 similar gates. I know how to size the transistors of a given gate for equal drive capability(i.e equal drive of pull up and pull down networks). Please help me in this regard. Thanks,

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