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1000 Threads found on edaboard.com: Transmission Gate Delay
I just got some great help on this forum to resolve a logic gate issue, so I thought I would try my luck with what I hope is my last issue. Below may be too much context and you may ant to skip to my "question" at the end. For background, the context is a battery management system for a 200 Ah LiFePO4 marine battery bank. The system has a
Dear All, I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error 157326 The script I am using to generate is as fo
In a prototype board for Lithium battery charge control, I have a three input AND gate (74LS11N). The inputs to the AND gate are: 1A = 5/0 volts from a digital output pin on an Arduino nano 1B = drain of an N-channel MOSFET (HUF76423P3) acting as low side switch on a 5 volt supply 1C = drain of a P=channel MOSFET (STP10P6F6) acting as a
I am stauding the MOSFET caharcterstics , May I get a Desgin for a MOSFET based Switch for ON and OFF . with least resistance and maximum current . Where I start ? I can choose any MOSFET so please help me?
Hi everyone, For a project involving multiple drones communicating to a single base station, I'm looking for a chipset (or alternatively a module) that supports a star topology network (i.e. multiple transmitters sending data to a single receiver). I need quite a bit of range (about > 2 km) with antennas that aren't ridiculously large since they
Let's say I have 5 NMOS with size W/L connected in series (stacked) with gate connected together, from what I understand this is functionally equivalent to a single NMOS with size W/5L. In terms of saturation check only the top NMOS will be in saturation while the other 4 will be in triode. My question is regarding this saturation check, specifica
Can someone please share nand gate equivalent data for TSMC22ULL & GF22FDX ..
Hey Guys, I am new to this forum. I just wanted some help regarding the Lt3750 chip. I have read the previous threads on the same.. I didn't want to reply on that since it is too old. I have designed my PCB for charging a 470uF 400V Cap with a 6A configuration 300V circuit configuration. I have followed the recommended design for the PCB and als
Doesn't work this way. With an ideal transmission line model (infinite common mode impedance), the circuit would work as a phase splitter. But infinite or reasonable high common mode impedance isn't feasible unless you place a ferrite core (transmission line transformer). L=100um suggests you want to implement the transmission line (...)
Hi, Gurus, I want a pulse filter to filter false signal. In my circuit, there is a reset signal. If I set the reset to low level with more than 100ms duration, my module will reset. Otherwise, if the duration is less than 100ms, I hope it doesn't. So that the false pulse, such as 10ms duration low level interference signal, doesn't reset my m
Can simulator like ncverilog simulates the metastability behavior of CDC circuits? How to do simulations with metastability models (RTL and gate-level)?
Why we used derate factor while calculating delay of a path ? and What is the impact of derate factor, if we do not consider at all?
Hi We have pulses which we need to delay by some approx. 280ns, and indeed we need to make the pulses shorter, again by some approx. 280ns The attached (ltspice sim and pdf) show two circuits which could possibly achieve this. Do you agree that the top circuit, which uses a logic buffer IC, is not workable in reality due to the high output impe
The primary current sense threshold of the LT1681 Two Transistor forward controller is 150mV max. Do you think this is too low (ie due to possible noise issues) for use in offline SMPS?s of 300 to 600W? Also, could the low sense threshold noise problem be in some way mitigated by using a current sense transformer rather than a sense resistor?
hi i saw in a file( i did not find the file again) that for layout of nmos transistor , two polysilicon layers was used for connection of gate to other segments. why two or more polysilicon is used for gate in cmos transistor layout?also why multi layers of metal is used for connection source or drain to other segment? excuse me if this questio
Hi, I used a controller dsPIC33FJ16GS504 for on gird solar-microinverter, in my hardware part when I applied input (24-dc battery not a solar panel), also connect lamp of 300 W as a load, and applied a grid to the output side as per given in document (for detail microchip document AN1444). I also read a procedure to start hardware. As per proce
i suggest you find the components that can achieve your transmission in air test it in air to be sure it works then move to water note that the wavelength of the light in water will change based on the index of refraction of water, about 1.33 for water add the various contaminants in fresh water, it will be a little different add the vario
Hi there, I wanted to know what all is there to know about synthesis of HDLs pls. I recently went to an interview and I was told that I don?t know anything about synthesis (I basically knew what synthesis in HDLs mean and could only translate simple behavioral models in logic gate circuits). Hence pls. tell me what all to know about synthes
My teacher gave me a problem below : Implement a serial transmission system, the system is described as following : - The system is divided into 2 parts based on their function : +) The first module receives data from users and send them to the second module through a single wire. +) The second module receives data from the first module an
Physical transmission Lines have some valid models for simulations and this validity has some limits as expressed ADS Warning messages.. Correct the TL parameters otherwise even the simulator terminates the simulation, the results will be erroneous due to those constraints.


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