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7 Threads found on Triple Gate
In SOI, device stacking (with a gate network tailored to suit, different depending whether you're DC or RF oriented) is the done thing. In JI you are pinned by the gate-body voltage in cheapo standard CMOS, maybe free your hand some with a twin- or triple-well process. I've seen HV DC switches done this way with an op amp driving the (...)
triple means the package includes 3 of these NOR gates. Positive means the gates are responding to positive logic states (high (or "1") is active, low (or "0") is inactive). Valid for inputs and output.
I am trying to design an op-amp with rail to rail inputs and am finding an issue with the symmetric input stage trick. I am limited to a process with no floating gate and nothing fancy like triple well. I have tried two approaches, one with a simple dual (symmetric) nmos and pmos differential pair and also with a dual folded cascode approach (se
We need to know the range of voltages you are trying to pass. If it includes the negative range, are you sure that your process has triple well capabilities to support it?
Hi... Has anyone has worked on TAB full bridge DC DC converter where power can be transferred from one port to another port by changing the phase shift of the square wave pulse to the switches of the bridge. I did a simulation but I obtained that power is transferred even when gate pulse sent to all the switches of the bridges are in phase. C
Hi gurus, Am new to this groups and novice in hardware stuff. I found that If (in protected mode) A20 gate is used to access odd megabytes. and is used to reset the cpu so that we can go back to real mode from protected mode. In another article i read that triple faulting also used to reset the cpu. 1. if present day OS boots at prote
Hi, all, What are the difference between (0.18um)high-voltage triple gate process and other process (typicallly used in mixed signal circuits)? I have seen dual gate process so that we can double the supply voltage so that we can have higher output swing...and so on... I understand that thicker gate process endures (...)