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# Two Phase Clocks

32 Threads found on edaboard.com: Two Phase Clocks

## resistor between two opposite clocks

Hi all I am investigating the response of a circuit in which two synchronous clocks with 180 phase shift are connected by two 10 kohm resistors and the output is the common signal between the two resistors. May anybody help please?

## Sync / Async clock domains -> how to define?

Hi All, I have two clock domains - clk1 and clk2. The clk2 was generated from clk1 and its frequency is 3/5 of clk1. Could these clock domains be considered as synchronous? If they are could not be, then why? Thank you!

## Two submodule with the same clock period, but with different root clock

keep in mind to check the phase of the two clocks.

## Clock Domains -> how defined?

113 views and no replies. Tsk, tsk. That's what happens when you post a vague question. Anyway, read this: (from a Cadence paper) "A clock domain is defined as that part of the design driven by either a single clock or clocks that have constant phase relationships. A clock and its inverted clock or its derived divide-by-two (...)

## set_false_path for static input

Hi, I have a circuit with two asynchronous clocks, one low frequency clock SCK is for programming the coefficients COEF in the instance ISPI at the startup phase. Once the programming process is finished, COEF doesnot change any more, the other instance IFILTER cadenced by the other clock DIV takes the values in ISPI/COEF an

## modelling two-phase clock in Cadence RC

Hi, My design requires two clocks. One clock which has a 90 degree phase shift with respect to the other (but with same frequency). During synthesis (with cadence RC) I defined the first clock as follows: create_clock -name clk1 -period 1000 clk Now how do i specify the phase shift for the second clock? thanks in (...)

## Break before make circuit..what is it?

Yes, I was relating to two phase clock which don't overlap, so there is no chance that both clocks/signals are high at the same time. But, I get your point..thanks for your answers As an example, think of a switched capacitor circuitry. This works only in case of "break before make".

## How to evaluate removal check for asynchronous reset?

I have removal check violation during timing analysis. When I looked at the report, the asynchronous reset goes to two flops, one is clocked by the clock twice faster than the other one. The two clocks are synchronous(same phase). While calculating removal check for slower clock, it is adding one clock period (...)

## Instantiate CLOCK in VHDL (Xilinx)

Normally, we using core-gen to generate a clock in implementation. DCM/PLLs are not generating a clock, they are deriving multiplied/divided/phase shifted clocks from an external clock source, usually a crystal oscillator. Without core genrator you have two options: - using external clocks directly - instantiating DCM/PLL (...)

## Scheme to select one of the two clocks

dselec The clocks themselves do not have any relationship in terms of phase and frequency. There are two independent cloks and we need a gate level circuit diagram that can chose any one of them depending upon the value on the selectionl line. The selection line is one bit. So the clocks are not multiplication or division (...)

## verilog code for phase detector

i need a verilog code for phase detector to detect a positive edge of two clocks i.e one fast clock signal and one slow clock signal, simultaneously and produce output as just a single pulse..i need it soon..pls help out.

## jitter question, synchonizing two clocks

Hello friends, Can someone give me a little advice? I have a (quite pure) sine clock at about 12MHz and I need to multiply it 10 times to obtain 120MHz square. The question is originally jitter is multiplicative? Do I need to use dedicated multipliers like those:

## Literature needed on Static timing analysis

This is one of my favorite links for a beginners guide to STA STATIC TIMING ANALYSIS also weste harris has some pretty cool slides on two phase clocks, pulsed clocks, edge triggered flops and setup/hold/time borrowing here CMOS VLS

## Need some comments on my VHDL codes for async FIFO

Hi, everyone! I'm a beginner at VHDL coding. Recently in a project, we need to transfer data between two clock domains. These two clocks probably at the same frequency but with asynchronous phase. So I use async FIFO. The attachments include the VHDL codes and the testbench (not perfect). I don't know if it is fully (...)

## clk synchronous design methodologies

How can i synchronous two different clocks from two different modules.plz help me thanks in advance

## Compareing two clocks in VHDL

Hello can anybody help me to give logic for vhdl code, which will compare two frequencies say f1 and f2 and also their phase, and giving o/p based on the comparison.

## Phase shifter or delay line

Hi all, I am working on a design In which I have two clock that needs to be in sync always, however these two clocks are from different source. I want to add a phase shifter or delay line in between one of the clock so I can adjust the phase difference after the manufacture of the PCB. The frequency of (...)

## Clock Phase synchronisation

Can we phase synchronize two out of phase clocks using RTL code. If so can anyone share me the design approach.

## Help me with chopper amplifier

Just use two non overlapping clocks to switch the switches on and off .hence the input signal will get modulated ie multiplied by a square wave n in the output again use a similar pair of switches to turn on and off which is equivalent to the demodulation operation.