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Two Stage Cmos Opamp

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21 Threads found on Two Stage Cmos Opamp
Hi, I designed an operational amplifier cmos two stage. I want to simulate the PSRR. Vdd = 2.5 V and Vss = -2.5 V, are the voltages supply of the opamp. What configuration and values in the input should I choose for the simulation of the PSRR ? Regards, Joaquin
We are designing a two stage cmos opamp using cadence 180 nm technology.We tried P E Allen Text book procedure but the output is getting saturated.We are not even getting the high gain.Can anybody suggest us the design which will give us around 80db gain.We need it for a comparator in SAR ADC.Please try to give the hand (...)
Hello- Here are the specs for the opamp I have: 180 nm cmos 1.8 V DC gain: 40 dB Gain at 20 kHz: about 30 dB Total current should be less than 10 nA With a two stage, miller compensated is this possible (assuming subthreshold bias at the NMOS inputs)? Any other ideas? Thanks, analogLow :roll:
hi, this is two stages full differential opamp:the input pair transistors of the first stage is NMOS, PMOS is its loadl; the second stage is cmomon source ampifier. I did some simulation,but gain cannot get to 88dB, I want to know if this topology can get 88dB GAIN using 0.13um cmos? (...)
The file attached is one of the best sources of information for two stage op-amps. I used it in a student project of mine. It worked vary well. Enjoy!
Analog Design Essentials, Sansen. Especially for two (or more) stage Miller OTAs!
I am new to analog design and want to practise my skills. can someone give me specs for 2stage cmos opamp design Thanks
Is is correct to use two different channel lengths in 2 stage opamp design ??? Sure, why not? I am using 0.18? cmos tech. I am using L = 0.54? in stage 1 and L = 0.18? in second stage. Will it cause offset ? Not if used in different stages. Yes, if done with (...)
i want to design a two stage opamp with cascode compensation, just as the picture below shows. i use the capcitor Cc for compensation between node A and C, my question is, how to choose the value of Cc? for ex: resolution:10bit clock:50M swing:2V Vdd:3.3 DR:70dB PM>60deg CL=1PF then how to design this (...)
Don’t use a two stage approach; you will burn too much current in the second stage. Unity Gain Bandwidth = 500 MHz => for stability second pole should be around 1.5 GHz!!!!! Second Pole = gm(second stage)/(2*pi*Cload), believe me that will cost current. Normally a folded cascade should be enough to reach 75 dB, (...)
Hello there, Can anyone propose good books or papers on the design of cmos operational amplifiers? I am particularly interested in the traditional two stage cmos approach (a differential pair and a common source with active loads). Please post any files or links
in PTAT reference, 1\the opamp has two terminals, why does the terminal of pnp with resistor connect to the positive end of opamp? pls explain to me clearly. 2\the bjt can use pnp or npn, why does pnp normally be used? what's the advantage of pnp (in standard cmos technology)? 3\someone says the (...)
Hi, Any notes or reference for designing single supply based two stage miller all cmos books the design examples are based on dual do i go about designing it for single supplies. thanks.
How to designa two stage cmos chopper-stabilized OP? I want to use in bandgap.
if common mode Vs of two stages are different or need to control independly
Hi. Is anybody of you have idea how to increase the loop gain in a two-stage opamp (cmos). My circuit is the simpliest two stage opamp. Now i have 55db and i want to reach 75db at least. Thanks one way is simply increase the gm of the first stage (...)
if you want to reduce 1/f noise, two techniques can been thought of--chopper and auto-zeroing.
In Razavi's bookcmos Intergrated Circuits>.The problem of 9.24 shows a opamp with two pair of input stage,a fast path in parallel wiht a slow path. What's the characteristics of this circuits? and Show me some papers about it ?
hi can some one help me how to design this project? STEP BY STEP PLEASE i should use hspice 1. Obtain the features below at lowest power consumption possible at FF and SS corners of 0.35um cmos. 2. Design bias circuits 3. Design proper switching CMFB for two high impedance nodes of OTA Target features of design are: Vdd=1.8 V DC gai
hi guys i m final yr student and doing a 2 stage cmos opamp design. i have completed the design of the individual stages of the opamp like the current mirror, diffamp etc, i want to know how to join/interface these two stages .i.e the op amp uses the amplifiers which r (...)