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51dB (voltage) gain is A=355 A=gm*Rout assume best case Rout=Rload Then gm must be 355/50K or 7mA/V If you can find a transistor with this kind of gm and decent Early voltage then a single CE stage could do it. If Early voltage is a problem then cascode it (CB over CE) Of course input impedance match will cost some base current so you will
Hello, I am trying to apply an adaptive biasing technique to source the differential pair of the fully differential amplifier, the adaptive biasing source a current of let say Ib under small signal condition. Under slewing or large signal behavoiral this current is increased proportionally to the input difference amplitude. My question, I alr
Hi everyone, As part of the course i took in analog circuit i required to design an amplifier with these values: Rin= 52kohm Rout = 53 ohm A=35 gain in db F-3dblow = 400hz F-3dbhigh = 400khz M1= 40db/dec M2 = -20 db/dec Dc supply voltage are : +5 v , -5v Transitors are ntype BJT My idea was using a simple CE amplifier with (...)
The battery in the video title photo is a very powerful Lithium Ion 3.7V type but the battery later on is a weak little (AAA?) super heavy duty carbon-zinc 1.5V type. The transformer is tiny. Few English words were spoken in the video.
Hi all, I'm working on a design that draws power through USB but needs about 1.5A of current at 5V. Hence I'm exceeding the 500mA limit and need to "negotiate" a higher current from the source. I've read various pieces of USB documentation and I understand a small microcontroller would be the way to do this properly. I'm looking for a solution t
Hello i am using the two stages amplifier shown bellow into the transimpedance feedback system shown bellow. if the system shown bellow i have miiler capacitor and feedback ressistor how do i break them into the system shown in the end? Thanks. 157371 157372
Hi guys, I have a schematic of OTA amplifier: 157362 I want to know the W and L that were used to design this OTA. I don't have more information other than the ones provided in this picture. since all transistors are in saturation, I thought about using the saturation current equation to find (W/L) ratio. by assuming
Hi guys, I'm trying to design a transimpedance amplifier for optical receiver, based on this acrticle: the requirements: -VDDA=1.8V -Cload = 200fF (the output of the amp loaded by 200fF) -the total gain At=Vout/Ipd = 3000, (Ipd is the current source on the left on the schematic) -BW>2
Hi this is a 80m SSB transceiver based on the phasing method I consider the phasing audio section. In the transmit mode, 180 degrees AF phase signals are provided by the BJT terminals, then somehow shifted by these RC to prod
Hi I have found this filter/amp combination, being simple with nice features. I wonder can I use other opamps like the ne5534 or is the performance specific to the 741 and will differ if using other opamps? Also how about Jfet based ones like the tl071?
I am working with gnss sdr software for processing rf signal captured in file. In gnss sdr software configuration the data source mentions adc sampling rate and type as i and q samples. Nothing is mentioned about IF frequency. Does that mean the intermediate frequency is always zero for I and Q components?
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How did you get R2+RL/1+Av? I'd like to adapt your technique. The one I know is too involved. Yours seems fast. Can you refer me to a literature that explains this type of method? Look for Dr.Middlebrook's Extra element theorem. or any material regarding that.
How to simulate ACLR of designed RF amplifier using ADS?
Would it be acceptable to post a PDF of a hand drawn schematic or is that a bit rude/disrespectful? Any kind of readable and meaningful documentation is welcome. General rule: Don't leave any input (used or not) of any IC floating. With "LS" type they may be pulled low internally. LS has input diodes and must be p
I have a open loop TF given by 2s+100/s^2. As stated in theory, type 2 system should provide zero steady state error for velocity inputs. Could any body explain the limiting factor of this velocity. I mean, what is the maximum velocity input that this system can track?
Hello, attached is the transient pic of the fully differential amplifier I have designed, if you look to the vo+ and vo- you will see the sparks on it, however the differential coltage is clear due to the subtraction, my question, should I be concirned about the individual outputs or only have to look to the differential output (Vo_diff)
D6 may have to be a fast switching type, possibly a Schottky diode but a 1N4148 will probably do. The actual output voltage is set by R5 and R20 but if I had to guess at the fault it would be either C20 or C35. The Ic manufacturer recommends a PC817 optocoupler in that configuration. They are cheap and plentiful. Brian.
Foundries and their PDKs are not to be trusted. If you want to discover how you're being led, try a simple simulation of key PCM devices that are used for WAT. Turn on process and mismatch, set up the WAT testbenches and see how many times your one transistor (of each type you care about) will fail WAT limits for things like VT0, IDsat, leaka
Hi everyone, For a project involving multiple drones communicating to a single base station, I'm looking for a chipset (or alternatively a module) that supports a star topology network (i.e. multiple transmitters sending data to a single receiver). I need quite a bit of range (about > 2 km) with antennas that aren't ridiculously large since they