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Hello all, Currently i am designing a 2.0kW Half-bridge LLC with center tapped secondary for EV Applications Input Voltage:- 400VDC Nominal Output Voltage;- 40 to 60VDC Output Current:- 35A Fs_min:- 91 khz Fs_resonant:- 151 khz fs_maximum:- 225khz (Short circuit protection limited) I am operating the converter equal to or belo
I am designing a traditional 1st order delta sigma modulator. I tried to find the input referred noise of the integrator and switching network (circuit is shown). I set vin+ = vin- =vcm & then I set v to be a square wave at a frequency fclk/2 (to emulate the limit cycle behavior of first-order delta sigma for code 0). This (...)
I'm having difficulty in understanding the VHDL template for FIFO my instructor gave to me. Below is the instruction: Using VHDL, Design a FIFO memory. Make it 8-deep, 9 bits wide. When a read signal is asserted, the output of the FIFO should be enabled, otherwise it should be high impedance. When the write signal is asserted, write to
Ohms law: I = V/R I = 60000/1000 = 60 Amps W = VI = 60000 * 60 = 3600000 = 3.6 MegaWatts Your resistor will probably vaporise (unless it is a 3.6 MegaWatt Resistor) Your multi-meter will vaporise (or if you are lucky, will blow a "thought" fuse). EDIT: only a "thought" multi-meter will withstand 60000 volts. A real multi-meter will vaporis
According to my understanding, nWave doesn't have a command line interface. It fact, it seems to be unnecessary. After all, debugging is an interactive process. Unless you already have a list of signals in your mind, which you would like to pre-load into nWave. If it's so, then you can modify signal.rc file and load it into nWave when you open the
Hi, Give complete informations. Show your schematic (not the one from the datasheet). Give detailed informations about supply voltages Give detailed informations about input signal voltage Give detailed informations about output signal voltage Read other "IR2110 problem" threads. Most problems are: * not keeping on input voltage leve
For understanding how to interpret data stream from Sartorius scale read the following: And, please, do a Internet search. It won't bite you
I'm trying to understand if the *.PININFO syntax is optional in CDL netlist. Does spice read that? OR is it simply for human understanding, like a comment? What about LVS, does LVS care about it? Does spice? Which tools/checks take it into account? For the tools that do take it into account, is it a mandatory attribute? Where can i f
I am studying the process of aging in CMOS. I have seen the concept of "charge trapping" multiple times. Can someone explain this concept, and how it affects switching speed? -Thanks
Looking for resources about making decimation filters to put after sigma delta Modulators. I know Temes book has some ideas, but are there any other resources for this ? I want to implement using logic using gates or verilog blocks. Do I just have to look at papers ? For example the Hogenauer filter which is covered in Temes book but look
For the following LDO circuit, how does the transient performance enhancement circuit sub-block in green color works
I have a lot of difficulty understanding certain functions and understandings of CST, I know frequency, reflection coefficient S11 and transmission loss But the image below shows what I doubt. If anyone has material that talks about each point it comes to each function. 157915
According to my understanding, set max fanout simply controls the number of nodes driven by each output port. It provides the tool with a guideline of how much fixing is still needed. But usually max capacitance is the only thing that matters when the load of a port is considered. Max fanout violation can be ignored as long as max capacitance is sa
I have some questions about 1) Why is skid buffer designed to be 2-entries FIFO instead of just 1-entry FIFO ? However, pipelining handshaking is more complicated: simply adding a pipeline register to the valid, ready, and
yefj, you have basic problem with understanding what common mode feedback does. It has no connection to mismatch of currents, CMFB sets/tunes both currents in a way that the main OPAMP will operate in the normal active region, it sets all transistor pairs of the differential circuit to the same desired operating point. If the currents have mismatch
Is it possible to have power line communication through several distribution transformer? The transceivers should be connected to 220V low voltage AC outlets with a communication link through a 11kV high-voltage line (delta-connected and without neutral) and through 11k/220V distribution transformers. Are there any commercial products available
Is there any cheap method to detect open circuit fault/broken conductor (high impedance) for a 3-phase Δ-connected 11kV lines without neutral?
What is the value and function of both v and vbar is this schematic at the vref inputs ? 157617
Hi Gurus, I try to have intuitive understanding of the field distribution in a simple microstrip. As the picture, it can't be simplied as a microtrip, and two wave ports capsulate its endings. The "solution frequency" is at 10GHz. The S21 is normal as almost 0dB from 0 to 10GHz. But the field is obvious un-even. At port1 it is yellow indicating
A grasp of RF matters really needs an understanding of phasors and vector based mathematics. Starting there will make this more sensible or just think of it as magic. - - - Updated - - - With RF sometimes 1+1 is 2. Sometimes 1+1 is 0. That is what makes RF so interesting.