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1000 Threads found on edaboard.com: Understanding Delta
Hi, I am having trouble understanding how a deboo amplifier works. I know how a Howland Negative Impedance works, but I can't understand the effect of the capacitor. Also why is the buffer needed in the input of the circuit? And does a DC offset in the input signal cause the op-amp to saturate? Thanks for the help, I appreciate your response and
156390 Sometimes the delta S value in HFSS is shown as N/A. What causes this?
Can you back to your university to attend the related classes? Then you should be able to learn this stuff within a year or so. With integrated circuit design, you need a much more detailed understanding of the device physics and technology.
Yes ,The Example code is to complex to understand thats the reason i am understanding from scratch.
Hello For a new design there is a vibration resistance specification of 7G 1000Hz log sweep 15 min/reciprocation duration 20hour. I'm really new to vibration specs. May i know how these spec can impact my HW board/circuit design. I understand for connectors -locable type, Thorugh hole , Flat Ribbon cable may withstand vibration better and
I am reading couple of books on calculating the values of VIL, VOL, VOH, VIH for basic NMOS inverter. I notice there are 2 methods to calculate these values. One is an approximate method: where it is assumed that VOL is basically equal to Vmin that a given circuit can achieve and set VOH to Vmax. Second method is standard method: to get the -
I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient microarchitecture for network-on-chip routers ? [B
Looking at a waveform without seeing or understanding what you're actually trying to do doesnt tell us a lot. So far, to summarise, you have asked - "My design doesnt work, whats the problem?" and so people have answered with very generic answers. If you want specific answers, you're going to have to ask specific questions and probably post some c
Hi, From the equation of cascade noise figure, we can see that the noise figure of the chain is determined by the first several stages of LNA. But how to physically understand it? Why is cascade noise figure set up bu the first several stages?
If, and that is a big if, I am understanding you correctly: You require three clamp type probes, a single differential high voltage probe, and a 4 channel scope. Connect the high voltage probe to channel 1 and set the trigger to that channel. Clamp the current probes to each phase and feed them to channels 2,3 and 4. Make sure that all of the
based on my understanding, treez answer is makes the most sense. question: buck-boost regulator or buck regulator? which one is more efficient Treez's answer: we need to see the regulator scheamtic. usually regulator will have FET as switches at the output. if the regulator have one FET at the output, it's the best because switching loss wil
Hello, Can anyone help me to know that is it possible to implement any ADC on FPGA board by using Verilog code? Or should i have to go through circuitry, and here i am not talking about implementation of onboard ADC or some external readymade ADC .
Hi, we measure stability of a circuit in terms of phase margin and gain margin in analog circuits where as for RF circuit analysis kfactor >1 and delta <1. In some way, is there any relation between these two?
For Efficient microarchitecture for network-on-chip routers , do anyone know how this round-robin arbiter actually works ? Note: The corresponding verilog codes seem to be located at
155796 I'm designing a switch in HFSS. I need some help understanding the results. The S parameters are for a switch in OFF state. I understand that S(1,1) nearly being 0 means that the switch is off and all power is reflected. What I'd like to understand is why is the curve shaped this way? and what does S(1,2) being equ
Hi, I want to measure phase voltage of bldc motor which is having delta connected system. Since there is no ground terminal in delta. I am confused to measure the phase voltage of motor with oscilloscope. Can anyone tell me how to connect the channel probes to measure phase voltage of delta connected motor?
Dear friends, it is know that shorter channel transistor is faster than with longer gate. This I can understand well when we talk about NOSFET working as a switch. But how this concept affect the speed of the operational amplifier where GBW = gm / CL for example. If you tell me that shorter channel leads to higher gm I can say that gm can be
Hi guys, First of all, I apologize in advance if my question makes no sense, but this is the first time I am dealing with an entire RF transmitter. For my research project in grad school I designed an RF transmitter that includes a digital baseband (SPI and SRAM for loading the IQ samples), analog baseband (IQ DACs and filters), and the RF front
Hi, I am trying to understand the connection between the two USB classes CDC and HID and four types of following data transfers. Control Transfer Isochronous Transfer Interrupt Transfer Bulk Transfer Is it possible to implement these transfer types in both CDC and HID USB class? Is it possible to achieve Full Speed (12 Mbps) in bo
For a 10bit resistor string DAC, if the INL is required to be less than 1LSB. Why the resistor mismatch delta(R)/R< 1/(2^9)? Why not delta(R)/R< 1/(2^10)? Thank you.