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8 Threads found on edaboard.com: Using Tcl Synopsys
Can anybody provide documents or links to see how scripts should be written in VLSI by using tcl?
Hi everyone, I am using Faraday-90nm library. My lib_search path for tcl file is /Cadence/libraries/Faraday-90nm-Faraday90nm-SP/Design-Kits/2010/fs0a_a//2010Q4v2.1/GENERIC_CORE/FrontEnd/synopsys/synthesis and the target library is fs0a_a/generic_core_ff1p32vm40c.lib. The verilog file is a accu.v (accumulator). I am using (...)
Hi, I'm using the PT(PrimeTime) and ICC(IC Compiler) of synopsys for timing closure. The "fix_eco_timing" command of PT is very powerful for timing ECO. Timing ECO script(tcl) which is generated from "fix_eco_timing/write_changes" command of PT is used for timing ECO in ICC. But this ECO script is for ICC, we can't use this script for (...)
A design has an address bus 32 bits wide of which only 2 bits go into a module. You create an extra level of hierarchy in DC using the group command and only 2 bits of the address needed go into the newly created module. DC brings in all 32 bits into the module and does not connect the top 30. Is there a way to get rid f the unused bus ports? Pl
Hi All; I am trying to optimize my design using Power Compiler (synopsys) and looking for Power Compiler' Usermanual and Tutorials. It seems to be not available in this forum and synopsys site as well. Could anyone give me some advices? Many thanks in advance. W3Y
I was trying to read multiple files in primetime. read_file -format verilog But this doesn't work.?? How do I use wildcards for unix files in primetime? Added after 1 hours 20 minutes: Found the answer: read_file -format verilog glob[/
You can also try the Advanced ASIC Synthesis using synopsys DC, PrimeTime and Physical Compiler book .. it's good and practicle
tcl user reference material: using tcl with synopsys tools---pdf chapter1--chapter 5