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112 Threads found on Vco Supply
Hello, does anybody know that why a resistance is made in series with the control coltage of LC oscillator and in which range should be this resistance? Thanks
Thanks Vfone&Klaus for your views and suggestions. - - - Updated - - - @Bigboss fc is 2MHz in this PLL - - - Updated - - - This PLL uses differential outputs,PD_up and PD_down,not the charge pump. OK, if PLL+vco does not consume much curr
supply your IC ( or whatever ) by a simple battery ( including Vtune Input if there is one ) and observe the vco output. 1.6GHz/V is a huge Kvco and you will never prevent the poor and dirty vco signal with this Kvco.It's not normal..
I'm learning HSPICE. When simulating a ring vco, I can't get oscillating wave. It seems to be locked,but i'm sure the connection is right for the netlist is available on Cadence Spectre. Is there any issues. Thanks in advance.
Hi all I face a strange issue when simulating the LDO together with a LC vco. I want to calculate the PSRR at the output of LDO connected together with the vco. I run AC simlation and I take quite strange simulations results( maybe dangerous) at the LDO voltage output. I attach you a screenshot for getting a better feeling about the possible
I designed a 2.5GHz CMOS vco,(core current: 20mA), Rout=300omhs, 3.3V VDD supply, Now core output amplitude is 1~5V. phase noise simulation is about -116dBc/Hz, test is only about -108, the layout, power line:-?, bond wire may all have problems. But now i want to know if 1~5V amplitude is too high. is it dangerous?
Inject 100mV or more of ripple into DC using a sweep generator to test sensitivity of f & Vac vs vco ripple. Then you will know how much DC filtering is needed such as with ferrite beads or RC or LC or better C's.
Many vcos are not really operating small-signal linear (e.g. CMOS current starved ring oscillators) and many supply-noise challenges are not really small signal analysis depends on all of the blocks' DC solution having relevance / decent frequency domain modeling. It's an OK place to start. But I think if I cared a lot about things lik
Many clocks that are RC based such as the old Dual vco TTL were supply sensitive because they were design to be Voltage controlled. The same is true of many one shots etc. Crystal oscillators will change frequency with supply due to input capacitance changing with supply voltage by a slight amount. Some clocks use (...)
Hi, I read a paper about vco design in an IC. It is 1.8 V supply. The vco frequency gain is 270 MHz/V. When I try to simulate in Matlab, I find it has problems. The 1.8 V has maximum only frequency range of 270 * 1.8=486 MHz. How can it reach 3.128 GHz of its goal? Is my understanding wrong? I cannot find another vco gain (...)
Hi.. i am using 28mn technology and have 900mV supply voltage.. i need to convert 0 to 800mV bias voltage into.. 200mV to 700mV i have 900mV MOS and 1,8V moses in my pdk.. which type of circuit shoul be used to achieve this..? thanks
Did you ever inspect the ring oscillator waveforms to understand how the current control works? There might be an unwanted voltage swing at the inner supply nodes. A standard vco technology uses differential stages, and if I remember right, voltage rather than current control.
I cannot see SA bandwidth and resolution settings. The spectrum shows a FM signal, so if you want a good oscillator, take care of its DC power supply. If your oscillator is a vco, take care of the varactor DC, too.
Hi, Thanks everyone for the reply. 1. I forgot to mention that this an injection locked oscillator locked to the the third harmonic of 800 MHz i.e. 2.4 GHz 2. The PCB has not been designed very well since it was my first RF PCB. The decaps (5pF, 1nH, 10nH) are far away IC pins. I shall design a new one though. RC
I have a CMOS LCvco with tail resistor only on top to provide bias current. Between this resistor and sources of cross coupled PMOS transistors, a big decap is added (~70pF). The vco can start oscillating at TT corner, but couldn't at SS corner. If the big decap is removed, SS corner can work. What could be the reason? Thanks in advance!!
Hi All, I designed a LC vco, I can simulate phase noise of vco, but I was asked to simulate phase noise sensitive to power supply decoupling. Any suggestion how to simulate? Thanks in advance. John
Dear guys, any advice and recommendations for low power & low supply output buffer for vcos?
hello, i am designing tail bias LC vco using tsmc13rf with supply voltage 1.2v and tail current 1.5mA @ center frequency =1.8G and iam using spiral inductors from tsmc13rf lib. and i have some questions: 1-when i did transient analysis i found that the single ended peak to peak voltage reach 1.7v !! (more than the supply voltage) is that (...)
We want to have on/off feature in our vco,as the vco we are using hasn't this feature, we deem it having through vco power supply. If there is tuning voltage still present at vco input when they supply to the vco is off,would it cause any damage to the vco (...)
multivibrator and other simple oscillators suffer from drift due to aging, temperature deviations and supply voltage variations. PLL resolves such problem with locking a vco with a low drift and precision XTAL oscillator(eg. tcxo). also by some modification it is possible to add modulation to the PLL but for your application I think DDS is better s