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15 Threads found on edaboard.com: Vcs Gui
Don't have vcs docu at my disposal right now. Inside it search for the error with string : UCLI-003
Hi, I am new to simulation debugging. I have a simulation log file which is having some failures. I want to open vcs in gui and want to dump the some signals of the design. What are the commands to open vcs in gui. Thanks, tyuga454
guys, I have a problem when simulating my design in Synopsys vcs. The simulation went wrong with all register contains X when I simulate my design in command line mode. But it run normally in gui mode (i.e, invoke vcs compile with -R -gui options). So what's the different between 2 mode simulation (any implicit options (...)
Do you mean vcs of Synopsys as the simulation tool? If yes... If you are able to successfully compile your RTL and TB, then in the compilation dir, an executable named 'simv' will be created. You can bring up the gui by the command: ./simv -gui & That is your DVE gui and you can also find the DVE command prompt.
Synopsys' vcs has a "show drivers" command (or maybe was simply "show" or "drivers") with a path to an object as a parameter. ModelSim/Questa has a similarly named command. Both are more easily used in the gui, via drag-and-drop or else by selecting the target signal in waveform window, clicking on the corresponding icon, etc. But I also recall you
Hi Friends, I have very silly problem. I am running some testcases in vcs. Some testcases are giving different results in gui mode and Batch mode. I want to know if such things do happen in vcs or am I doing some mistake. Please help me in this regard. Thanks in advance!! Veeresh
Hi, I my design i am having a MDA reg . I am dumping whole design during my simulation( non gui mode) and after simulation i load .vpd in dve waveform viewer but it doesn't show me MDA dumped. It says None of the children of the object MDA is dumped. Can anyone help me in solving the issue. Thanks, Ashish
// Command line % vcs -sverilog test.c -debug_all; simv -gui; // This only shows SV portion :-( // C Code (test.c) #include "svdpi.h" int mult(int x, int y){ return x*y; } // SV Code (test.sv) program main; import "DPI-C" mult=function int mult(int x, int y); logic a,b,result; initial begin
I'm using vcs with the "-cm line+cond+branch" option; however, I am having trouble figuring out where the coverage numbers are reported. I ran ./simv and then tried using vcs with "-cm_pp gui"; however, I am not seeing any of the coverage values. I tried vcs with "-cm_pp batch"; however, I'm getting some errors about this (...)
I am using vcs ntb for small project provided in the Synopsys Tutorial.i want to ask can i use interactive vcs gui to debug my vera testbench with verilog DUT.i can to it in vera using vera_cs but how can it be possible in vera
Hi, I am trying to generate the VCD fille (VCDplus.vpd) for my simulation. I am using the following commands: vcs -debug simv -gui I am able to view the waveforms in DVE, however I notice that the VCDplus.vpd is not there. This file will be generated when I replace the -debug to -RI. May I know is there a way to use DVE
yes. In simulation, after getting wave forms, how can we see this dellta delay? And is delta delay equals to clock to q delay? vcs & MTI provide a way to do this in their gui as: "Capture Delta Delay" HTH Ajeetha, CVC
hi: Now i convert my simulation platform from modelsim to vcs of synopsys, but i can't find the gui of vcs, is there only command line style? thanks for any reply clive
There are 3 kinds of logic simulation: Event-driven compiling mode Cycle-based You may refer the simulator manual (ex. NC-HDL, vcs, ...)
Excuse me, except vcs, is there any simulator tool support vera-interface?? Vera use PLI interface to other simulates. :)