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26 Threads found on Verification Interview
Hi everyone, I applied for a job as layout engineer. The job spec are the following: DUTY: -schematic to full custom layout translation -layout verification and DRC -floor planning for optimal die area -generation of wire bonding diagram for assembly approval before the tape-out REQUIREMENTS: -EE degree with focus on microelectronics -g
I am new for the layout. I was asked below question during the interview, "there are two seperate gnds for digital and analog, VSS-D and VSS-A, in the layout. how does the layout pass LVS and Calibra?" May I know how to approach it? Thanks in advance.
Hi i have one interview question.....? how you verify your mod10counter.....? how u write test cases and verification plan for u r mod10 counter.....? i need exact answer for this.......?
In order to start any design, write down all assumptions into a "Spec" so you and others know what you forgot to assume or assumed wrong. Define Scope or boundary of spec, environment limits, inputs , outputs, process behaviours (time delay, verification) , user feedback outputs, , fault tolerance and detection, fault recovery and power initial
Hi guys, I have an interview coming up for the design verification team at qualcomm. Could any body here please let me know what kind of questions usually qualcomm asks for that position. Or at any other company in general. Also what probable topics I should be focusing on? (I tried looking for them here, couldn't find anything concrete) Als
Hi All, I have a t'con with Sasken for verification Engineer. Though i have attended few interviews with other companies for the same post, i want to know in particular about Sasken. So anyone who have attended earlier or working for the same can help me in this. Thanks in Advance:-D
Since you are interviewing for a DV job, I would suggest brushing up on System Verilog and have a rough understanding of the verification methodology (choose one of VMM/OVM/UVM). Don't memorize it, just understand TLM, BFM, and what sorts of abstraction these methodology is designed to provide. Terry
assertion is a verification method for us to find some abnormal sequence very quickly!
Which one of these designs is most suited to use formal verification instead of simulation completely (not hybrid approach)? -Multipliers -MPEG Decoder -Arbiters -CPU The property "If a request is received, a grant will eventually be detected" is a: -Liveness Property -Safety Property -Don't know "Blackboxing" is to e
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i am in IV year, ti is coming in my college, on what topic i should concentrate,please help me! my branch is e.c.e. Is it for VLSI? If so brush up Verilog/VHDL. If you have any higher level verification experience like E/SystemVerilog/PSL that will be a GREAT advantage. You may also consider our internship program at CV
Thank you very much for response. I understand that you are giving almost complete exercise to the design but can you tell me that what would be coverage ? and how would we get satisfied that the verification is done.
Hi every one, Yesterday i got an interview with NVIDIA. They asked one intresting interview question. What if design engineer and verification engineer do the same mistake in Test bench BFM and RTL(DUT)? How can you able to detect errors? My answer: Some bugs we can able to detect in FPGA. But he is not convinced (...)
New batch of "Advanced verification with System Verilog" is starting on 24th Dec 2011. Get in touch with us at Home Hello every one iam hemaja mtech vlsi student searching for vlsi based job can any one suggest the openings or companies, sin
Hello all, I have an interview with Synopsys for a AE position (AMBA product line). Can anybody tell me what do they look for. ? Also I need advice on AE positons in general. I have been working as a design engineer for almost 4 years both in RTL and verification. The experience has been decent, my questions ; 1. Is a transition to AE a good
Hello, I am looking for Question bank (along with answers) of FPGA. This is required for answering job interview questions. Pls help me. If any has such document for FPGA/ASIC/CPLD/VHDL/Verilog/verification, Please let me know the link to download or mail me to Thanks, Vishwa
Hi, I will be facing interview for verification engineer job with a client. Can anybody please tell me what questions to expect and what are the answers. Thanks in advance
Hi all, Can anyone share some question and answers for asic-fpga design interview or any questions/answers for digital design. I tried looking in this forum but most of the topics point to the same 10-20 question in the internet. Is there any standard document which you could share ? I would really appreciate your help regarding this.
this book may be useful to you which describe how to use E to verfiy desgin.
Hi, I came across a advertisment for hardware design eng. it says: 1. hardware/PCB design for RF applications, inc PA,ADC,DAC,BPF,antenna.. 2. RFIC performance test, bench verification and parametric characteristics. 3. antenna and indoor propagation analysis, FCC and EMC compliance testing. For no. 1 what interview question can i exp