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14 Threads found on edaboard.com: Verification Ram
Hello I have users with unsupported OS who have asked for the cadence package. They want to run it on a virtual machine. I want to manage their expectation. Has anyone experienced running simulations/test on virtual environment? What was your experience? My concern is whether cadence software will run as they expect (like that on a desktop/se
DO you have enough ram? How many processes are running in Task Mgr under all users? 50? 100? Run lean for best results. Did you try compatibility mode install with latest version? I'm just guessing. Ask the experts
I am working as pcie verification engineer for quite long time. Any query, Q&A and discussion regarding pcie protocol or verification are welcomed here. Regards, jdshah
hello... am supposed to implement a 8051 open core (verilog programming) into a Xilinx spartan 3e (xcs3500e) board and verify the implementation with led blink program.. i have implemented the core into the fpga successfully though ISE and iMPACT... My question is how can I load the blink program into the device?? This blink (...)
Hariharan.gb The idea of performing LEC is do a verification of RTL with the GLN (Gate Level Netlist) after synthesis. Hence during synthesis the memory models are not synthesized and are only macros hence to avoid their compare all memories, analog blocks and non-synthesizable constructs RTL constructs are treated as notranslate. Also your RTL w
"Verilog tesbench for ram Model" You may take a look on some memory models: "...A synchronous write sparse memory model, written in VPI - C-Programming interface to the Verilog HDL. sync VPI memory ..." VHDL, verilog, design, verification, scripts, ...
This might help you: "This page has links to some memory VHDL models, which I used for simulations. 1. An asynchronous, written in VHDL, sparse memory model to reduce memory consumption..." VHDL, verilog, design, verification, scripts, ...
Try to modify the code at: memory HDL models... VHDL, verilog, design, verification, scripts, ...
This may help: This page has links to some memory VHDL/verilog/vpi models, which I used for simulations. VHDL, verilog, design, verification, scripts, ...
A simulation model can be seen at VHDL, verilog, design, verification, scripts, ... . Look for async vhdl memory.
A low-level description of the readback capture feature is described in chapter "Readback and Configuration verification" of Xilinx UG071 "Virtex-4 Configuration Guide". I haven't seen any software support for this feature, so you may need to create your own tools for capturing and parsing the data. Also, I think the technique captures the entire F
I do use the calibre for the layout verification. But it becomes difficult to rectify the DRC errors looking at the DRC.db (error database having x-y co-ordintes). Does anyone have any sort of interactive (GUI) for DRC debugging for the calibre in Skill/perl? Thanks in advance Sooraj S ram Added after 50 minutes:[/
I do use the calibre for the layout verification. But it becomes difficult to rectify the DRC errors looking at the DRC.db (error database having x-y co-ordintes). Does anyone have any sort of interactive (GUI) for DRC debugging for the calibre in Skill/perl? Thanks in advance Sooraj S ram
You should minimize changes between FPGA and ASIC. Partition the design such that modifications are made only to necessary modules, eg. specific cores, ram modules and clocking logic. Like what 'cbh1024' said, write your code as portable as possible. It will greatly minimize the verification effort.