Search Engine

270 Threads found on Verilog And Cadence
Describe correctly This CTRL block is written in both verilog-A and verilog-D code. when I perform an spectre simulation The ADC_testbench simulation is running okay,It can't be true. cadence Spectre can not treat verilog-D. but when try to run it on AM
Hello all, I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors: Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSYS_UNCONNECTED__0". Error: (DB-270004): Illegal bus reference - Can't tap "
Hello all, I want to design a model of a MASH 1-1-1 ( 3rd order sigma delta modulator) in verilog A. I am new to verilogA and i am having trouble designing it, especially the delays of the error cancellation network. Any help will be greatly appreciated. Thank you in advance
cadence Spectre can not accept verilog-D. You have to use NCSim with AMS option which is called as AMS Designer. Or legacy VerMix(=spectreverilog) which is a cosimulation between Spectre and verilog-XL might be available.
I have a question for the following statement: I was checking logical equivalence between verilog and .lib using cadence conformal As I know LEC is done between similar files, VHDL vs VHDL or verilog vs verilog. (When you get bronze netlist is not the final one, still designer may expect changes in (...)
Hello, I am new to ASIC flow started working on cadence front end tools. recently i came to know about tsmc nanometer libraries (.lib) for synthesis purpose. Like wise I am hearing some other libraries like "timing libraries" , "verilog .v libraries (not RTL)" and "simulation libraries" etc., apart from synthesis libraries. Someone (...)
This completely depends on your flow but in general when you finish P&R you'll end up with a netlist and a .def file (or a gds, or something else but .def is the least problematic in cadence tools I think). So what you can do is you can import the verilog netlist as a schematic (or just netlist), and you can import .def as a (...)
Hi, I have written a verilogA code for a track and hold circuit. I simulate it (by using the symbol view) and it runts properly. Is there a way that i can handle a circuit or work at least some layout from the code i have written? Is there really an analog circuit behind my code or is it just the code running ? Thanks
Hi, I have loaded a verilog file in cadence virtuoso in which i implement an 8 to 3 an input i have an 8bus the code i used an array with 8 bits for input and 3 bit for output.I want to run a test in the schematic.How can i give an input with 8 values??
Hi , I need to add a third part component to cadence,this component is written in verilog. This component is placed in a website compressed in a zip file. unfortunately I don't know which are the command in linux in order to get in internet downaload the file required and add to cadence. In windows, the (...)
Build FIR filter model using verilog-A. You can find many examples in "rfLib" of cadence dfII.
Hi all, I am working on a DFT . its an academic project where iam using cadence tools - genus synthesis solution (formerly RTL compiler) for DFT and Encounter test(ET) for ATPG. now the question is, after performing DFT synthesis, i was supposed to write ET scripts which were used by ET for generating testpatterns with the command : (...)
Not that I've seen but a pair of vpulse sources is not that challenging to set proper parameters for, if this is for Spectre analysis. and there are, I'm sure, some verilog NOCG code snippets loose on the InterWebz for the searching.
guys please help how to write and simulate verilog code in cadence? thanks in advance
I want to use verilog.inpfiles.flattened from schematic which has some behavior view and has `include definition inside. The problem is that virtuoso flatten netlisting seems to fetch contents inside `include definition instead of just leave this `include on the netlist. That causes my netlist a mess and somtimes can not be used for (...)
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use the cell from the foundry library there are (...)
Hi, I want to build a SAR ADC. I am starting from behavioral level. The comparator is described in verilogA and the SAR logic in verilog. Can I use spectre simulator for that or do I need another simulator environment for that? thanks a lot for helping
Hi, I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a verilog-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them floating. I tried different verilog-a lines but the code always fails. For example, I tried using the following line that I (...)
Hi! i wrote verilog code for low power test pattern generation and i have to apply the test pattern for benchmark circuits and calculate fault coverage how to find out fault coverage in cadence tool kindly some one help me
I have written a verilog code for a circuit (test.v) and a testbench (testd_tb.v).I use these commands for generating the power using cadence encounter RTL compiler. I have made 3 folders. Work,RTL(where all .v files are stored), Library(which has slow_normal.lib). In the work folder i type these commands (...)