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Verilog Back Annotation

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10 Threads found on edaboard.com: Verilog Back Annotation
Hi all: I am using Cadence SOC Encounter to extract the post-layout netlist and SDF file. I wrote a testbench in verilog and I added the sdf_annotate command with itput arguments as my SDF file and my top-level instance name. Then during elaboration using the following command in NC-Sim:: ncelab -work worklib -cdslib /home/achundur/mu
SDF back annotation works in relation with verilog model. SDF should included the net delay or more detailed the path delay, and the cells delay.
I've read numerous similar threads but I still can't get this thing to work. The verilog design is a DFF with asynchronous R and S (dff.v). I have created a testbench in order to simulate the DFF in ncsim (dff_testfixture.v). I would like to back annotate the testbench file (dff_testfixture.v) with the timing data (dff.sdf) extracted from the r
this is mainly meant for back annotation. The `celldefine and`endcelldefinecompiler directives tagmodule instances as cell instances. More than one pair of `celldefineand`endcelldefinecompiler directives can appear in a single source description.Certain PLI access routines use cells for applications such asdelay calculation. verilog-XL (...)
you need Cadence IC445 tool, SOC encounter, synopsys tool, virtuoso GUI or GDS of Analog block. Once you get .lib file,library compiler can be used to get .db file. Now the Design compiler/primetime can be used to read .db and get verilog file by back annotation. ---------- Post added at 10:27 ---------- Previous post was
Hi, I tried to run post-P&R simulation in ModelSim with SDF back annotation but it failed due to some syntax error in the SDF file. The Place & Route is done by Encounter and then saved as the verilog netlist. In Encounter, I used both the delay calculation in the Timing menu and the command "write_sdf" in the command line, and (...)
hi frndz, i am suppose to use `celldefine in verilog and do a coding but i dont have any idea about this other than the fact that this is to do with the library cells to be accessed and mainly meant for back annotation. Can any1 help me with a few examples of how to use this. thank you
Hi everybody, I am stuck in a very odd spot in my tool flow. I am working on some asynchronous modules which is working with synthesized synchronous module. i am able to generate the sdf file using Design Compiler, but i am not able to back annotate this sdf for testing in Modelsim. I have tried it with NC-verilog, but its also not using the sdf
I'm trying to backannotate SDF into a compiled ROM. The verilog for this ROM has the following timing variable: $setuphold. The SDF out of primetime has $SETUP and $HOLD. When I run ncverilog I get a bunch of the following errors: I'm sure that PT has a way to write a combined SETUPHOLD check though I did not check
Hi incisive, Your meaning specify the hierachical timing check in the verilog simulator or select different ways to do timing check in simulator? Please clear it.