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11 Threads found on edaboard.com: Verilog Based Projects
Hi, I need a c code for testing the full functionality of my Risc-based microcontroller designed through verilog HDL. Apparently i need to write a c code which totally occupies the RAM and uses whole general Instruction Sets of PIC16f8X mirocontrollers. I wonder if ANYONE could help me out.
Hi, I'm in M.Tech final year , i'm interested in Digital design particularly using verilog coding. Please can anybody suggest some innovative projects so that it will be helpful in future. waiting for some ideas.
projects such as this are a frequent topic. See the list of related threads further down this page. Try a search on 'verilog spwm', or 'fpga spwm'.
The behavioural models need not be register based. You can define cells as registers in verilog and then assign them in always blocks without using clock. Furthermore, I hope you want to build this system only for simulation. You cannot do a synthesis/P&R operation as you will need the exact memory models from the memory vendor.
yeah you can start, designing projects based on pic and avr micro-controllers. and after getting some experience u can easily work on verilog hdl system.
Hi, I am new bie in VLSI world, I need a suggestions from u guys regarding FPGA project(verilog based). i would like to develop my own proto board.
I want to clarify one thing from you, what is the sdram u r using, if possible send me the data sheet of your sdram. most of the cases there is no need to change the verilog code since it is already optimized. you need to check what configurations u have given in the verilog coding like row address column address burst rate like that.
Was dr... I have over one year experience of working in verilog and FPGA Kits (Both Quartus and ISE) and have done several projects including one major project of designing OFDM PHY... I can teach you through the initial stage of entering into the design work. I also have extensive computer based FPGA material... Let me know if you (...)
i need verilog code for any of the following projects...plx share... 1. Linear Predictive Codes 2. Fpga based PLL 3. Digital Oscilloscope On FPGA 4. Implement a Processor (DLX, MIPS, RISC) In verilog HDL (16-Bit Processor, 8 Registers) 5. Accumulator based Architecture Processor 6. Implementation of (...)
How about VeriWell verilog Simulator?? Have you tried this!
HI IF YOU R INTERESTED TO DO EXPERIMENTS WITH CPLD AND LEARN VHDL AND verilog CLICK have a nice time bye