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Verilog Code For Receiver

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10 Threads found on Verilog Code For Receiver
In my project I want transmitter to be ON for 0.5?s and receiver should be ON for 1.5?s for that pulse generation please help me with verilog code in which I want switch between transmitter and reciever using a multiplexer my making use of this pulse generation code. Thanks (...)
Do you know any VHDL or verilog ?
What is baud rate. I don't understand it completely. All i know is, it act to slow down the clock for the data transfer or am i wrong about this. How can write its verilog code for the baud rate generator.
I am going to implement the sphere decoding algorithm for MIMO receiver on FPGA. Does any one have a VHDL or verilog code for that? If you have any C or matlab code this will be also helpful.
HELLO .. I want to test my transmitter for AWGN .. i have coded my transmitter and receiver using verilog hdl .... kindly if anybody has verilog code for AWGN .. where i can change SNR values .. and calculate BER for each SNR.....any suggestions (...)
Hi Im doin a BPSK transmitter/receiver using verilog... my lecturer wants us to do it by using another work as reference but im yet to find any work of BPSK... we were asked to do improvement/modification on the previous work. any idea of how to get a code/paper/work on BPSK? Thanks
hii can anyone..send me matlab code or verilog code for rake receiver using multipath channel tracking..... here is the architecture of rake receiver for which i'm trying to implement please help me out.... .... thank you
hello can anyone plz send me matlab code or verilog code for rake receiver...please mail me to thank you
or where can I get it? I want to start from a simple example for my recent project. thanks
this is code for uart receive but in verilog from xilinx app note module rcvr (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ; input rxd ; input clk16x ; input rst ; input rdn ; output dout ; output data_ready ; output framing_error ; output parity_error ; reg rxd1 ; reg rxd2 ; reg clk1x_enable ; reg