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48 Threads found on Verilog Dac
Dear all, i want to generate 1MHz, 2MHz, 3MHz square wave in a parallel manner. and i want to increase or decrease the voltage and frequency for individual square how to design in verilog. hi, you can produce n number of square waves using your clock..for that, what is your clock frequency and you can
Hi, I have a requirement to define an output with a more 'analog' feel then the straight forward digital definition that I currently have in place. dac_out is defined as a digital output This is simply 1 or 0 based on: ------ module dac (IOUTN, IOUTP, VDDA1V8,, BIAS, CLK, dac, ); inout (...)
hi I have completed my M.Tech in VLSI Design from C-dac, Mohali. I have knowledge about verilog, system verilog, OVM UVM methodologies, AHB\AXI protocols. Is there any opening of VLSI Engineer. Before this i have 2 year exp. in industrial automation(PLC,SCADA). Plz reply what should i do now
Is there a way to simulate a digital to analog converter in ModelSim????? I have my verilog code that produces the 16 bit input to a dac . It would be really nice if I could somehow see the analog waveform in simulation...
I've created a dac using veriloga(the code is below). My question is which function can I use in veriloga (in digital verilog the function posedge is used) to save the V(out) value only at the rising edge of the control signal? module dac_verilog(ctrl,b0,b1,b2,b3,b4,out); input (...)
I am no expert on this topic, but I can give it a try. You can connect the output of your ADC to a ideal dac (verilog-A model or similar). You can then extract the simulation waveform of the dac output and calculate INL and DNL. I personally prefer to write verilog-A models for both dac and an INL/DNL (...)
My hspice 2008.10 can run normal simulations. However, when get to verilogA models, it will complain something weird. During .hdl command processing, loading verilog-A modules from './'. hsp-vacomp: hsp-vacomp: Invoking the verilog-A compiler for (...)
Hi, Can any one suggest verilog code for sawtooth wave form.? thanks for spending time for read my question.
Hello all, I have a continuous time (CT) third order delta sigma modulator that produces SNR=98dB when the circuit noise (thermal and flicker noise) is not considered in a transient simulation. When I use transient analysis with transient noise in Cadence-spectre, the SNR drops to 60dB. Replacing the circuits with verilogA modules (noiseless mod
i having problem with my verilog dac..can anyone help me plsssssssss... module dac5(clk,reset,dac_mosi,dac_sck,dac_cs,spi_ss_b,amp_cs,ad_conv,sf_ce0,fpga_init_b); input clk; input reset; output dac_mosi; output dac_sck; output (...)
verilog-A Sample Library - Analog/Digital Converters and Modulators
I was wondering where I can find a tutorial that demonstrates the linking between verilog and verilog AMS in SMASH. Moreover, is there any pre-developed converter module ( ADC, dac) that I can use in SMASH? Even tutorials of Spice + verilog that use multi-bit ADCs and dacs would be very valuable. I already (...)
i have designed adc,dac and comparator in verilog-a. Now i have to simulate them by using hspice but i m not getting netlist for it.please help me out to get the netlist for this three modules...
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an ADC chip as one of my course projects. actually i want to design a chip that works as and ADC if the mode pin is high and dac if its low. plz gude me out, and suggest me that if its a nice project or not? and will a person having little ver
Hi I am studying Mtech VLSI design, and am in my final year. I am searching for project topics for my final project. Can anybody suggest any IEEE projects, or any other project ideas? I am interested in Digital design, VHDL, verilog. Any help will be apreciated.
Since it is not a very complex logic block, just do it by hand! It will simplify your design flow. You could use verilog-a to speed up the simulation but you will be adding only something like 80-100 gates to your design, so almost no speed impact...
check here You can find the models you need.
Hi all, I'm new to FPGA and verilog. I have the Xilinx startes kit and I want to communicate from FPGA to dac section. dac needs SPI proto. to get initiated. Please let me know how to do that. I have user guide from xilinx and in that it has got good details about the protocol, timing dia. everything.Bu t I'm not able to implement in (...)
yes, it's possible.. I implemented a BPSK modulator in a spartan 3E fpga, only with verilog and schematics designs (that could be translated to verilog)
You could also try to model things that are not critical to bandwidth or accuracy, more simply. Like, the front end logic probably could be verilog or veriloga. And of course for top level type simulations the whole dac could be behavioral most likely. Knowing when to fight, and when to fake it, is key.