Search Engine

Verilog Delay Function

Add Question

1000 Threads found on Verilog Delay Function
I have cooler master silent pro defected after thunderstorm, there is 330v DC on main big condensators, also 5v stendby present but all other dead. There is no power VCC to IC cm6806+X, (I think this is used for PFC) 10pins smd. There is also 8pin dip (pin6 missing) a6069h Any help,schematics or else will be welcome Thanks
char font = { {0x7f, 0x08, 0x08, 0x08, 0x7f} // 48 H , {0x7f, 0x49, 0x49, 0x49, 0x41} // 45 E , {0x7f, 0x40, 0x40, 0x40, 0x40} // 4c L , {0x3e, 0x41, 0x41, 0x41, 0x3e} // 4f O }; void test_2(char *str) { int i, column; for (i = 0; str != 0; i++){ for (column = 0; column < 5;
Our application is Advanced Drive Assist Systems(ADAS). Our Electronic Control Unit(ECU) contains Two Renesas RH850 / U2A16 Microcontrollers. Our Embedded Software Design is based on ETAS Autosar version 4.x RTOS. Two Renesas Microcontrollers communicate with each other over Renesas High Speed Serial Interface (RHSIF). Communication is full dup
A port has a direction, kind, range, datatype, and a name. Everything except the name is optional. Systemverilog has an elaborate set of implicit defaults for the first port, and subsequent ports. They are somewhat convoluted so Systemverilog extensors remain 100% backward compatible with verilog. If you
Hello everyone, Suppose we have a Fractional-N frequency synthesizer employing an MMD + 3rd order MASH loop. If we want to divide by the fractional value 100.XX ( where XX = fractional value ) , the MASH will instruct the MMD to divide by values between 97 - 104. My question is , which is the maximum delay for a new division value to be loaded fr
Hi, I would like anyone interested in these topologies and/or with practical experience or knowledge of both SEPIC and Zeta to share their opinions. I read that SEPIC positives are that it is more efficient, has lower input ripple; negatives are two RHPZ, high output ripple. Zeta positives are no RHPZ (easier control loop compensation and hig
A logic gate is an idealized or physical electronic device implementing a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary reversible logic, Toffoli gates are used.
I want to put a delay in my code to wait for a random number of seconds before going forward. I'm new to C and coding in general so I tried to patch together two example functions I found (random and delay), but so far it's not working. This is what I have so far: // generate a random number between 1 and 5 int random() { int
I tried using seekg but it didnt work. Im trying to read a specific line(like 3rd line) by getline function. When i use seekg i cant even read from the start(i tried seekg(0)). It would be great if anyone can help.
Hi, I've installed the Cadence software and a new hitkit in local in Xubuntu 20.04, but when I try to run a simulation with Pmos the following errors appear in the log file: Error found by spectre during AHDL read in. ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file
Hi, I've installed the Cadence software and a new hitkit in local in Xubuntu 20.04, but when I try to run a simulation with Pmos the following errors appear in the log file: Error found by spectre during AHDL read-in. ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//92a8e845bfcfac352c9dbd
Besides spectrum analysers and oscilloscopes what other equipment is needed to be learned to perform testing Analog ICs and blocks? And who defines the standards for such characterization tests? IEEE? (I would like to hear especially from who has been in such a lab)
Hi, I'm sure I'm not the first who ever asked about the problem of plotting a 3D farfield exported from CST MWS. However, since days I try to get a reasonable solution with mesh(), surf() and plot3() in Matlab. All of this does not work. I found a function that does the job: patternCustom(). But I do not have access to the Antenna Toolbox, so I
Your question isn't very specific, what do you want to achieve? VHDL and verilog are digital simulators without means to represent analog signals or sources. I can imagine a discrete noise generator as part of a digital signal processing test bench, it could e.g. use the pseudo random function UNIFORM() in IEEE.MATH_REAL and possibly digita
Hi , I am new to hspice I want to plot delay vs. load capacitance I am doing .TRAN 1p 100ns sweep Cload 0f 10f 0.2f $linear sweep this is and .MEASURE TRAN delay TRIG v(A) VAL='HSUP/2' FALL=2 +TARG v(X) VAL='HSUP/2' RISE=2 this just prints the rise delay for different load point sweep Is there a way to plot this (...)
I think you answered your own question. The only fos synth tool is yosys and that only works with verilog and older xilinx devices (and its only around because someone reverse engineered the bit files they use).
I often have test generation problems where I need multiple function Generators capable of generating Sine, Ramp, Arbitrary , Square, and synched to each other in some cases. This is a single chip solution, each onchip DDS feeds a WaveDAC that generate the desired waveform using DMA and lookup tables onchip. The DDS are capable of FM as we
Dear All friends I have a simple microprocessor core. I want to add some memory mapped IO to it. Is there any sample code (verilog) for this type of IO? Or any implementation suggestion? THX
Why failed ? always @(posedge clk)
Recently downloaded a memory model for DDR4 memory from micron's website and found that they have converted their models into System verilog Interfaces. I'm ok with that... however, I still need to put a wrapper around it to make it work with mixed VHDL/verilog-2001 simulation. I'm not really sure how to correctly connect the inout ports from