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Verilog Delay Function

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5 Threads found on edaboard.com: Verilog Delay Function
Hi All, Due to absdelay function can't support AC simulation, so I use transition function instead. I just want to delay the signal from the previous block, not redefining the rise and fall time. But I found after changing to transition function, the results from transient simulation seem not correct. (...)
I wrote a verilog module in RTL and use it to abstract high level clock gating function. I want to replace it to a ICG cell in synthesis in order to ease DFT and PR flow. But when I tried with Magma, the tool complain 'no delay node found, won't do any clockgating'. Anything do I miss or any mistake exists in below code? module ClkGate (...)
I need to generate a long delay without using # , wail or for???. Maybe A function that i will call once for a small delay say 5min or four times for 20 min im looking for a long dealy Any ideas please ---------- Post added at 19:20 ---------- Previous post was at 19:06 ---------- verilog synthesizable l
Hi all, Can anyone kindly provide me with a verilog-A/AMS model of a voltage-controlled delay line? I know this is a DISTRIBUTED component, but there might be a good lumped-model approximation for it. Thanks, Ahmed
In verilog, the most important difference between a task and a function is that a function cannot consume time (delays, blocking statements, or call a task). Additionally, a verilog function must return a value, and the value must be used, as in an assignment statement.