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Verilog Delay Sdf

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17 Threads found on edaboard.com: Verilog Delay Sdf
Hi, I need help understanding the single delay feedback fft architecture. I'm attempting to write a verilog code for radix 2^2 fft. I have gone through several papers but none of them have in depth explanation. Please help Thank you
Hello, every one. I find my ncsim can only simualte the sdf file in precision of 10ps (round to 10ps) For exampe,This is a simple BUF sdf information: (CELL (CELLTYPE "BUFCLKHD30X") (INSTANCE U10) (delay (ABSOLUTE (IOPATH A Z (0.263:0.266:0.266) (0.257:0.259:0.259)) ) ) )
sdf back annotation works in relation with verilog model. sdf should included the net delay or more detailed the path delay, and the cells delay.
dc will provide the netlist in verilog format (more usual) and you used the verilog description of the std cell as well to execute the simulation. but you should also add the sdf or be carefull of the delta delay during the simulation....
Hi We are at the process of simulating a gate level post-route verilog netlist using ncsim. We see a few INTERCONNECT information in the sdf file that shows negative delay. While elaborating we get the following warning code (sdfNDP): An attempt was made to annotate a negative delay value or pulse (...)
As I know you just need to add delay unit part in your verilog or vhdl code not in modelsim.
I have created layout using cadence SoC encounter. I have saved the netlist .v file & delay file .sdf. targeted library is faraday 180 nm. Now for doing postlayout simulations using modelSim I have added this netlist, .sdf file, lbrary files which are in present in the generic core directory by folder name verilog. but (...)
Library.v comes from tsmc or its standard cell library vendor (ARM is the one of the standard cell library providers). Since you've already got your .lef and .tlf, I assume you have downloaded the library somewhere. Just go there and look for the verilog model.
Hi Guys, I am simulating verilog model using an sdf file which cotains delays between (a,b) and (a,c) The verilog model is containing this specify // delays (a=> b)= (0,0); (a => c)= (0,0); As you may know the real delay between (a,b) and (a,c) in sdf will (...)
Hi, I tried to run post-P&R simulation in ModelSim with sdf back annotation but it failed due to some syntax error in the sdf file. The Place & Route is done by Encounter and then saved as the verilog netlist. In Encounter, I used both the delay calculation in the Timing menu and the command (...)
how to implement radix22 sdf fft using verilog.
I have generated pattern with TetraMax .But ,at present I still don't get a sdf file for simulation with NC-verilog. I want to know how to simuate without sdf file and get a right result ?
Use verror command: Owner@cvc ~ $ verror.exe 3438 vsim Message # 3438: A non-zero INTERCONNECT delay is specified from a source output lower in the hierarchy to a destination output higher in the hierarchy. verilog-XL treats such an INTERCONNECT delay as a delay on the drivers of the source. ModelSim adds the INTERCO
Hi friends, I currently verify the whole DRAM circuit using verilog. For analog circuits, I have to write models for them in abstract level. I now verify only functionality not timing. The delay of all components are predefined and not precise. I am thinking to use sdf or SPEF files for better performance but I do not have any experience. (...)
As for congestion.. I'm not overly sure as i've only used SE with older 3 metal 0.5um libraries which congestion was never a issue.. As for delays, etc.. i just create a sdf and bring it into the verilog simulator to see timing.. REPORT delay FILENAME "routed.sdf" ; jelydonut
i have to check the standard cell verilog model on the "specify" parts. can you give me the exact timing difference between the two paths, and the detail logic of the path. thanks Added after 37 minutes: i checked verilog model. with no sdf, "specify" model are used, which is totally inaccurate. w
Hello guys. How do u make adjustment to testbench ( rtl ) to verify that the verilog netlist ( from dc or fpga ) that backannotate with sdf is correct with the rtl simulation ? Once u synthesis with dc/fpga like xilinx . You with have gate delay ( sdf ) . How to make proper adjustment to the pure rtl testbench for the (...)