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Verilog Encoder

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68 Threads found on edaboard.com: Verilog Encoder
Hi I disgned 128b/132b encoder and decoder block in verilog code but my data width is 8 bit and my encoder' s input in 128 bit so how can I communicate my data bus with encoder?how can this encoder get 16 8 bit symbol?
Hey new to the forum and i need help with a project i have de2 boards and i need to have one board encode a message and the other board decode it and display it on a the 7 seg leds we have the encode/decode code but not sure how to get them to talk
Hi I want to design 128b/132b encoder and decoder.I got the verilog codes for 64b/66b encoding system but I dont know how should I use it for 128b/132b? Do you have the verilog code for 128b/132b?If no, please help me to write the codes
Goggle for "verilog 64b/66b" and get many hits, e.g. Xilinx application note XAPP687.
Hi, I am trying to design 64-6 priority encoder using verilog-a, so I started writing a code for 8-3 priority encoder for practicing as I am new to verilog-a. I tried the following code but there is a syntax error in "code=3'b000" line. How can I assign the the output of the encoder? module (...)
i am doing project on turbo codes so if any one could help me for sending me the verilog code
i need to implement rpm measurement in fpga, plz help me writing the code for above function
i am doing a project of convolutional encoder with viterbi decoder with K=7 AND r=1/2 also using FPGA for implementing i need verilog HDL code of it and i have more doubts about this project....please kindly help me to doing this
Doubt in port mapping: How to port map the following module in verilog. The encoder has the input as x and output as y. Now the decoder obtain the input from encoder by port mapping. The decoder has the input as a and output as b. Now how to port map the y and b.
Hello Mates , I'm in deep need to generate a LDPC encoder and Decoder Module in Verillog OR VHDL for FPGA Implementation. Also 64-QAM Rectangular Modulation in HDL is required , can anyone help me out ? Regards Santhosh Kumar Thanna
I think this homework assignment is meant to teach you how to use tasks in verilog. See this tutorial for some examples:
hi saqib malik i need verilog code for turbo encoder and decoder using verilog pls help me.. send the code to my email :'(
iam doing my project in vlsi and i need an verilog coding for encoder and then decoder and my specification is (255,223) :|
Hai all I am doing project in verilog HDL, I need Reed solomon encoder and decoder codings.pls...help me.... thanx in advance.
Hai all I need the verilog codings for Reed solomon encoder and decoder urgently.
I am doing a home alarm system project in system verilog. I am using a 12 bit keypad input to enter the 5 digit password. Each digit is encoded by an encoder and then finally it compare with the original stored the password. My question is how will we input digits? Do I need to input each digit during positive edge of clock cycles? Do I need to
Hi I not saw the encoder 8b/10b in C but this encoder in verilog is here. I looking for 64B/66B or 128B/130B.
Hi, provide the other specification like constraint length K and G vector values. for complete guidance you can contact me through my email m_arsal4@yahoo.com hi, i am working on the project named fpga implementation of convolutional encoder and viterbi decoder using verilog. i hav done the encoder par
What exactly are you trying to encode and decode? Do you just want to, say, connect three switches as inputs, and use the eight LEDs as outputs? I don't see any particular problem with your code (does it synthesise? does it work?) though I find the verilog case statement easier to read.
The below is the verilog-A code for 8-bit thermometer to binary encoder. `include "constants.vams" `include "disciplines.vams" module bin2thermTC2BC(TC, BC,CP); input CP; voltage CP; input TC; electrical TC; output BC; electrical BC; parameter real tdel = 2p from [0:inf); parameter real trise = 1p from