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88 Threads found on Verilog Floating
Hi, I need a c code for testing the full functionality of my Risc-based microcontroller designed through verilog HDL. Apparently i need to write a c code which totally occupies the RAM and uses whole general Instruction Sets of PIC16f8X mirocontrollers. I wonder if ANYONE could help me out.
Unless you reading decimal number strings in your verilog code, there won't be a decimal number format used. Please reconsider. Number formats with decimal point used in digital processing are floating point or fixed point. Possibly constants are specified as decimal numbers in your code.
Not a real LVS. Few of the Ports might be floating (based on your verilog) But to confirm this, Run LVS with Calibre (or any sign off) tool
Hi, I have a vector and a matrix of hexadecimal values stored in .mem files. I need to subtract this vector from each row of a matrix in each clock cycle. I have read my files to my testbench file using $readmemh in verilog. How can I subtract them now? I have used xilinx ip floating ip core for subtraction as well. Here is my code but this c
Hi, I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a verilog-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them floating. I tried different verilog-a lines but the code always fails. For example, I tried using the following line that I found while (...)
If you want b to have the value 'b1111, then just do b = n; $realtobits returns the simulator's internal representation of a real/floating number. It's only purpose in verilog was that was the only way to pass a real value through module port. You would then use the $bitsto
Hi guys, How can I modify my FIR filter to have an input and output that have a precision of 3 decimal places. I already constructed floating point computation but I dont know on how to link it with my filter in verilog. This is my code for FIR filter: module FIR_filter #(parameter STAGES = 4) ( input CLK, input RST,
i have to design an adder module in verilog; input values are 0.1519 and -1.02123 You don't want floating point arithmetic you want to implement fixed point arithmetic. The whole point of using floating point is to be able to represent numbers like 0.0000000000000000234 and 234000000000000000 in a small number
hi, I am trying to write a code which will recieve real values from the real time enviroment.but verilog does not support real value synthesis, so how will i write a code in such situation,i don't want a truncated form of the real number suppose 2.3145 >2(this i don't want). so how do i process real value in the codeE?
Unfortunate the floating point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL. For the same reason, wr
I would also add CORDIC algorithm and look-up table (optionally with linear interpolation) to the candidate list. Of course it doesn't matter if you are using verilog or a different hardware description method.
Hi. I want to know how to handle of floating point in verilog. for example, 12.341 × 73.928 How do you usually handle of floating point in verilog? In my case, I just take 10000 times to each them. but this problem is not accurate. so I need your usually methods.
I am trying to implement a floating point multiplier on spartan3E using verilog. And I want to display the result in LCD(spartan3E 16x2 LCD). How can we convert floating point to integer format in verilog? How can we display the floating point number in LCD? And also I wand to give input to the (...)
I'm trying to implement a linear programming problem on FPGA. I have used real data type to generate floating point numbers. The program compiled fine, but when I'm trying to synthesize it for my Xilinx Spartan-3E FPGA board it shows error that real is not supported by verilog. It seems that we cannot use real for synthesizable codes. So any sugges
Hi, I am trying to do a code for do division using verilog that is work with fpga. The thing is division operator is not syntyhesizable.I am using fixed point arithmetic to represent a number (includes fraction),think the only methode to do it is loop baised substraction methode or quotient remainder methodeIis there any other possibility ?
Hi, I need to implement floating point arithmetic in verilog. I am aware of the fact that verilog does not support floating numbers. Any hints on implementation of floating point arithmetic in verilog would be appreciated. Thanks!
Hi, after running RTL Compiler I get a verilog netlist without vdd! and vss! ports. I think the reason is the .lib library that does not provide them for the standard cells. (but they are declared in .lef). Im not sure if this is a problem or not... When running Encounter after init_design I do the following: (Power pins are initialized by "se
hi, I am trying to generate IEEE 754 floating point IFFT using Xilinx ipcores and verilog, but it is giving fft of the patterns as the answer, I tried by putting fft_inv=0 varying fwd_inv_we ='1' and then fwd_inv_we ='0' but i didnot get the proper answer. do anybody can help me solving the problem ..?
Assuming the file in like : .1 .12 .15 .2 .26 .3 and so on write code like this integer in,i,out; real data; initial begin in = $fopen("input.txt,"rb"); out = $fopen("output","w"); if(!in) $display("File Open Error!"); if(!out) $display("File Open Error!"); i = $fscanf(in,"%f",data); i
verilog is not a programming language it is a hardware description language. What you've written is a program (something you would do in a testbench) that is not synthesizable as it can not be realized in hardware. Even without using real types the for loops won't unravel correctly in hardware. You're coming from a purely SW background, right? You
I think Xilinx used to have a verilog->VHDL converter. check their website.
Hi, I want to write verilog code for floating point to integer conversion... Can anybody help me have any materials? If u have can u pls send to me?......
Hi, I have a project on writing a n*n matrix inversion by using verilog code. I hope can doing this by using QR decomposition. Can anyone give me some clue on: 1) how can making the code is suitable for n*n matrix by just changing the parameter ? 2) a module that can do floating point division.
Hi, You have to consider using fixed point implementation (or floating point implementation) to handle the decimal number with points in your initial verilog code to make it synthesizable by the synthesis tool (such as ISE). Consider this tutorial:
Hello Sir/Madam, I have Spartan6 FPGA SP605 Evaluation kit. Using IP core generator, I wrote the program of floating point addition/subtraction program and I downloaded into the kit. But I have problem regarding to display result. So, plz suggest me a solution for that. One more doubt, How can we give the input value to HDL program??
I need help with conversion from floating point decimal to binary and viceversa using verilog HDL, on Xilinx or Altera platform. I want some suggestions regarding methods or algorithms that could help me with the conversions. Thanks.
I am doing mini project on floating point arithmetic unit. So please post code written either in VHDL or verilog otherwise give some links related to this...
hi...i currently working mu final project that would need me to use this conversion. Here what i'm trying to do: 1. let say i have this number in decimal 6.23456. I want to multiply this value with other value (integer) and display the result ( in fraction num) on seven segment using verilog code. for example: value a=6.23456 value b=6
A.o.a: In verilog HDL programming,I got some floating point arithmetic's to perform.I need to multiply a floating point number but problem is I am confused how to write verilog code that reads number convert it to fixed Q n.m format ....I know all the basics of Q n.m but problem is the algorithm behind this (...)
Why are you using a verilog testbench with a VHDL entity? wouldnt it be easier to stick to one language?
Hello, I need to 1. convert integer to fixed point 2. Then perform functions such as division and exponential equation Do you know any library or function for this? I know about mega functions but that is for floating point and it will require alot of resources that will be needed for other computations in my system Thank you,
Hello, I know there is the $realtobits and $bitstoreal. But that is for double precision. I need help in converting from integer to floating point (single precision). Are there libraries for that in verilog? Thanks in advance Chika
Hello, I am working with an equation Y= 1-exp(-a/b) a and b are inputs (integers) from a different module in my verilog code. Y is output a/b ranges from I working on a exponential algorithm that requires floating point as an input My question is, how do I convert 'a/b' to a floating point representation . So I can use that
Hello, What is the best way to read a textfile that contains decimal number (eg. 2.987) into verilog? At the moment, I convert the values to hex using matlab (using num2hex). But when I use readmemh, it assumes that the 32bit variable is a 'regular' number and not a floating number? Any suggestion will be greatly appreciated. Thanks!
Dear all I am implementing a algorithm of kurtosis in FPGA. I need 64 bit division in that. Can anyone help me in this regards ---------- Post added at 04:59 ---------- Previous post was at 04:58 ---------- in FPGA means in verilog. sorry for that
Most design compilers support mixed mode, VHDL components can be instantiated as modules in the verilog code.
but...i need the to divide the ieee754 binary floating point....because i need to write it in verilog.....
can anyone help me how to coding for this 2 step....using verilog.......please help
HI, I am Masters Student. for my project purpose i need some floating point calculation. but the input is in 16bit fixed point value. I need to convert this 16bit fixed value to IEEE64 bit floating format. 7380H = 0111 0011 1000 0000 convert into 0 (100 0000 1101) (1100 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000) can any
Hello All! Is anybody aware of where can I find the "University of Guelph floating-Point Arithmetic" library - "uog_fp_arith"? Is it free or not? How can I use it? Google seems to be not very friendly regarding this information. Besides, I am interested in any HDL package (preferably in verilog) that involves IEEE 32 bit single precision fl
e_xk1={1/8}; and e_xk2={-1/8}; 1) what are the resulting values in binary in e_xk1 and e_xk2?? 2) how are they calculated? 3) what should be the correct declarations for e_xk1 and e_xk2?
Hi, How can we design a divider so that the we can preseve the value after decimal point in verilog HDL Ex: If we need to divide the 3'b100 by 2 we will do it by right shifting 3'b100 by 1 time. if we need to divide 3'b100 by 8 we will do it by right shifting 3'b100 by 3 times. But we cant preserve the value after the decimal pont ie., 0.1 in
The first step is to implement the floating point unit. Then, you use the butterfly structure to make the FFT. For to start in floating point unit: and FFT
verilog/vhdl required
floating point alu verilogcode
i am doing my project in verilog..there i want to do calculation using floating point kindly anyone reply me how to represent floating point numbers in verilog....i will be very thankful..
I have a confusion involves the SNR comparison of DSM simulated in MATLAB and VA. In MATLAB, I can get the theoretical maximum SNR (88dB) using transfer function blocks and quantizer block. But in VA, it gave me 68dB (I used the laplace transfer function in VA to create my loop filters, and quantizers and DAC are 16 levels). I don't understand why
Hai all, What are the various checks that are to be perfomed on prelayout verilog netlist by physical design engineer , before implementing P& R . Regards, KVB
Hi all i want to implement the following mathematical equation in verilog: slopeup=(y2-y1)/(x2-x1) slopeup after calculations will be like 0.01456... or -0.013478......... etc. Plz can anybody tell me how to accomodate numbers like this in verilog???? Plz reply soon. Waiting