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Verilog For Statement

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121 Threads found on edaboard.com: Verilog For Statement
Hi, I am very new to this forum, so please pardon any decorum that i may have violated. Here is the reference code : always @(posedge clk or negedge resetn) begin if(~resetn) begin for(int j=0; j<64; j++) enable_data <= 1'b1; end else begin if(data_accepted) begin: ENABLE_DATA_BL
I have a question for the following statement: I was checking logical equivalence between verilog and .lib using cadence conformal As I know LEC is done between similar files, VHDL vs VHDL or verilog vs verilog. (When you get bronze netlist is not the final one, still designer may (...)
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks genvar
As for the second question, logical and operator in verilog is &&. Regarding first, presume you can see that the parameters are defined twice. We can't - without the code.
Hi. When I use initial statement in interface block in systemverilog, it have some compile error. Can't we use inital statement in interface block?
for (i = 0; i < 8; i = i + 1) begin test = array;// What is the operation performed? end What operation does 8*i+7-:8 perform? This has nothing to do with SV it's straight up 2001 verilog. The slice defined by: 8*i+7 -:8 results in bytes of a larger bus and.... Well it's a
Hi everyone, I am designing a FSM machine that controls speed configurations of my step motor. It is ALMOST done, however this bug gave me no other choice but posting it here. I can provide more code if wanted. //Speed indexes parameter _40 = 11, _20 = 10, _10 = 01, _0 = 0
@(posedge ticker) is not synthesizable, it's only used in simulation testbenches as an event control to wait until the rising edge of a signal. for edge triggered logic that is synthesizable you have to use always @ (posedge ticker) if you want to synthesize the module. This is a bad design as ticker is used as a clock when
Google it..you will u need it in vhdl only or verilog is also ok for you ?
Here is the code I created module clk_24hours ( output reghr_time, output regmin_time, output buzzer_mode, input clk, input hr_adv, input min_adv, input mode, input set_time); input alarm_is_set; output hr_selected, min_selected, ahr_selected, amin_selected; input [1:0
I want to use the for loop inside generate statement to be infinite as shown below. But the problem is I cannot stop or quit the loop at some condition using "disable text". neither i am able to use keyword "break". It is showing an error: unexpected token: 'disable' unexpected token: ';' please help me by solving
hello i'm new here and a beginner in verilog i have problem about scanning 3x4 keypad in verilog 117867 above is question now i already have 4-2 priority encoder to put row&column into keypad scanning and then put data into binary to bcd converter but now i'm stuck here. because i dont know how to put data
Looks like assert is the only statement you need to take care of. Several options: The "who cares" option. Any decent simulator will handle SV these days. So if your simulator supports SV you could just use SV for your testbench and verilog for sysnthesis. The "oh alright, I will Read The Fine Manual" option. Read the SV
HI all! I understand that the force command is not supported by synthesis. Is there any way to write it in the DUT? Or is there a way to force a signal (without using the force command) inside the DUT without writing it in the testbench instead write it inside the DUT? THanks...
Hi, I am writing assertions for some of the sequences. I want to update a register after an assertion is covered and use the register value to CROSS with an other register value, Can you please guide me on the implementation of the above problem statement. Thanks, Rahul
Hi You still don't sound like you grasp what a generate statement is used for in verilog. for most designers, these are not frequently used. Generate statements exist to a) save you from having to repetitively type similar states and/or b) having the ability to conditionally add code to your file. (...)
sun_ray, do you ever do a search for any of your questions prior to asking? I guess you don't like to expend the effort and want others on the forum to search for you. I normally just ignore all sun_ray posts (I think I need mrflibble's post eradication tool), but I thought looking this up and finding a good resource (...)
Hi friends, I need to know about the conditional operator clearly. Even though i do some of the examples as mux using conditional operators. But i didn't understand wat actually doing in the below code.. module rumania(gate, D, Q); parameter Bi = 16; parameter prop_delay = 0; input gate; input D; output [
You can easily create a generate for-loop for the outer for loop that creates 60 concurrent initial blocks, and use a counter to make the contents execute serially. Don't even need Systemverilog genvar i; integer j, k; for(i=0;i<60;i=i+1) begin : static_loop; initial begin k = 0; (...)
but i'm using Cadence Virtuoso (verilog ams), and when i use if statements, the simulator just blocks Verify syntax for verilog if (index > 0) if (i > j) result = i; else // else applies to preceding if result = j; The conditional statement (or if-else statement) is used to make a (...)