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Hello, i'm new with using verilog code, and i have a task. Making a timer with input:clock, reset output:seconds,minutes,hours. and i can't solve this, anyone who know the code help me. Your answer help me a lot. THANK YOU
Unfortunately I can not do it. I am using the 180nm TSMC library and they don't give the layout of the digital cells, just blockages and general cell sizes. I already did this, It was the first thing I tried was to do a gate-level timing simulation with the sdf info. Everything works fine in the simulation. The only
Hi, I learned there are 2 ways to read designs when we do floorplan. 1. read_verilog... 2.import_designs ... ddc .. I wonder (1)What's the difference between these two ways? (2) initial floor plan info generated from DCT is contained in ddc, is it also contained in verilog? So many thanks!
Hi, I learned there are 2 ways when read designs before placement in IC compiler,(after DCT) . 1. " read_verilog" 2. "import_designs .ddc" What's the difference of this 2 ways? Initial floor plan generated from DCT is contained in ddc, is it also contained in verilog?
Use $table_model() in verilog-A. If you use Keysight ADSsim, use Data Access Component.
Hi, I would use 2 ps/2 (mini din 6 pin) ports with only one FPGA. The signal "clock" can be the same for the two ps/2 ports? Can I drive the pins 5 of ps/2 connector with only one FPGA pin?
I am a newbie with the Raspberry Pi. I want to measure Temperature Reading in 12/16 bit resolution. can someone guide me how CKT should be designed and How can read value using software. usually arduino read analog voltage from 0-5VDC & rasberry pi will read analog voltage from 0-3.3V For better resolution we can use MCP3008 /MCP4725 series m
Dear my friends, I need to learn about bluespec systemverilog very urgently. I know it is very similar to verilog. But could you provide me some good material to learn bluespec? THNX
i am reading the book COMPUTER PRINCIPLES AND DESIGN IN verilog HDL so like Exercises in chapter 14 Design a computer system that contains a CPU, instruction memory, data memory, character RAM (text mode), font table, PS/2 keyboard interface, VGA interface, and an i2c controller with an i2c EEPROM, and develop a simple editor that deals (...)
Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in attatched file. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware). Also whe
Actually I am working in an DSP alorithm, in the top module of my verilog code I called my data as given in below code. But when I am dumping bitstream in the FPGA Basys 3 kit ( LEDs as output) the FPGA is not showing any output. Why? can anybody help me to solve it. (It is working properly in the simulation phase but not in hardware). Also when I
I have Intel FPGA MAX10 – that is what I am planning to work with. So a CPLD, which is much larger than a PLD. You'll probably want to do as wwfeldman posted and read the data sheet, but you'll probably also want to get a book or read an online tutorial on VHDL or verilog/Systemverilog as a way to write t
Hello All, I'm using dsPIC33FJ32GP204. I'm kind of newbie and sorry for the easy mistakes first of all.I 'm trying to do my research. I wrote a code that in CCS C works well for PIC16F877 using i2c that communicates with eeproms and lcd. But when I copy paste it to the dsPIC33f ( changig with device id) when i use proteus and when I set the dsP
Hi guys, I had been practicing a few problems in verilog and got stuck on this : Question : write a program so that output should be 1 when 'x' is greater than or equal to 'y' x and y are binary My logic module: module comparator( input x, input y, output z); assign z = ~y + x ; endmodule[/
The post body doesn't match the title. Where's the verilog code?
Only the last one because verilog/Systemverilog loops are unrolled at compile time. They represent multiple instances of whatever is in the loop and not sequential operations. You also have a typo as there isn't any signal called idx_to_flip. I also would not use an always @(*) for doing this, I'd put this in a task or create a test FSM to ru
i wanted to drive data and address from axi slave to 8 bit register, anyone can help me out with code or logic
Hello, I am designing a protocol as a part of my project. I did the interface part and now I am asked to do the CSR coding for master and slave separately. I don?t know where to start with. Can anyone explain what CSR is and how it works for master and slave so that I can move forward with my project?
As mentioned by betwixt, always link related threads 1. I tried, it works, it makes a sine wave from a quarter of a sine wave, but no internal RAM is used, RAM Can't be used, apparently. Partial RAM tables (e.g. quarter wave) can be used,
Hi all, I got access to the TSMC 65nm PDK. However, my tech lib provider didn't provide CDK for using standard cell libs in Virtuoso. They just gave other types of std cell files that can be used in other tools than Virtuoso like SOC Encounter, RTL Compiler, etc. The std cell files I have now are : 1-celtic (.cdb) 2-lef 3-tf 4-milkyway 5-