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1000 Threads found on edaboard.com: Verilog i2c
Hi all, I got access to the TSMC 65nm PDK. However, my tech lib provider didn't provide CDK for using standard cell libs in Virtuoso. They just gave other types of std cell files that can be used in other tools than Virtuoso like SOC Encounter, RTL Compiler, etc. The std cell files I have now are : 1-celtic (.cdb) 2-lef 3-tf 4-milkyway 5-
Not directly with verilog/Systemverilog. I think the lack of updates to the file isn't inherent in the system tasks themselves it's more of an OS think of when it writes out to the file during the simulation run. I notice that files I generate update but only after a significant number of KB's of output have been generated. You could write your
hi i need verilog code for my sequence 01 2 3.....................63 1000000000............0 0100000000............0 0010000000............0 0001000000............0 0000100000............0 0000010000............0 0000001000............0 0000000100............0 i need shift register code. This 8 bit should move one by one till 63 and
Hello! Thanks for your replies. In the meantime, I tried, and could have the result I wanted. I made a table of 1024 16-bit values: reg sine; Then I made a script to fill them all, and if I access sine and sin, then I get a sine and a cosine on the scope (I have wired MAX5875 DAC at the output of the FPGA). So a
i am using cadence IC 6.13 virtuoso to design an ADC i am trying to measure the SNR of that ADC , so i build an ideal DAC using veriloga and take the output of the ADC to the input of the DAC and then i took the output signal from the DAC and export it to the calculator of the Cadence and then i used the spectrum function to find snhr. there
Hello! I'm using Quartus with verilog. I have made a design that works, but as it becomes bigger everyday, I have to start splitting it into modules. Now I have been reading books about verilog and made some experiments, but unfortunately it never compiles, there are always errors. What I did is as follows: 1. The working code I m
So i am changing the usb hub controller in my project to a Microchip USB2514B since it was the 2nd cheapest on Farnell that fits my requirements and has great extra features i might want to implement like a custom configuration via i2c EEPROM. Link: Da
#2 I've noticed vpi handle in the vhdl standard? What is this? Is this the way the software processes the rtl code. Can you talk to modelsim/questasim or whatever software using these functions? VPI is from verilog
hii friends, This is code i have written for combinational parts of s27 circuit. i think it is not the exact procedure to write plz help me wheather it is correct or where i am getting wrong. module s27(G0,G1,G17,G2,G3,G5,G6,G7,G13,G10,G11); input G0,G1,G2,G3,G6,G5,G7; output G17,G13,G10,G11; wire G14,G8,G15,G12,G16,G9; not
Dear Friends, is it possible to use some part designed by verilog or VHDL with other schematic circuits ? for example I designed a three bit digital counter and I want to put this counter with the other elements like operational amplifier and resistor to build simple flash converter. I have tried to do it but the the simulator is refusing
Hello, I have the auto generated CRC parallel verilog code for muti-bit data stream. I even wrote a testbench to check the CRC. Now I want to write a testbench that injects random errors and detects it. How can i do that in verilog?
If I create a verilog cell, is it ok to attach it to the technology I use in my circuit (like MOSIS, etc..) or I must attach it to different kind of libraryIt has no meaning, unless you have layout view. by the way this editor from Virtuoso is not allowing me to copy and paste the code fr
In many standard cell libraries, supply rails are not shown as wired pins, but embedded as global named nets in the lowest level schematic (if schematics exist at all, in that library) or in the text based gate description (e.g. verilog). Maybe you are looking for "vdd" when you should be looking for "vdd!" (global power net). But I don't know
Hello, I am trying to implement verilog (actually: mixed VHDL and verilog) project for matrix multiplication from this WWW input and output data
Hello everyone, I have recently accepted a new position in academia and I am looking to hire several PhD students and postdocs to get my lab up and running. There is a very specific profile that I am looking for. These are some of the skills that the ideal candidate would have: - ability to describe digital circuitry in verilog - abilit
A reg used inside an always block leads to the inference of a flop. You use it when you are defining sequential logic. When you are writing RTL for combinatorial logic, something outside the always block, use wire. Think of wire such as simply connecting one electrical point to another. Please read a good verilog book, a real book, to clear f
Dear all, I am trying to synthesis my verilog code to check the slack. But the timing slack shows unconstrained. Attaching the declarations in my top module and constraints file. 154202 154203
I am trying to use PCA9539 as an IOexpander for my project. I have a STM32F103 connected to PCA9539 via i2c. The problem I have is to write into PCA9539. Based on the datasheet I should to send (1) address (2) command byte (3 and 4) data bytes via i2c. When I check the i2c bus lines with oscilloscope, I see the micro only sends 2 bytes (...)
Hi guys! First thanks a lot for your replies the other day, it allowed me to progress a little bit in my "after five" experiments. This time, I made a program for a signal generator. I have designed a board for it, but in the meantime I wanted to try, so I wired a R/2R ladder and I'm using a 16 bit output. Here is a picture of what it looks l
There's no generic format for fractional numbers in verilog. You have to specify a suitable format according to your requirements. Binary fixed point is the usual choice. It involves a rounding error when representing decimal fixed point numbers, but it's effective and fully compatible with signed and unsigned binary integer format.