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Dear all, When i tried to synthesize my verilog code in ISE, my timing report said, Minimum period: 4.490ns (Maximum Frequency: 222.712MHz) Minimum input arrival time before clock: 4.358ns Maximum output required time after clock: 0.728ns Maximum combinational path delay: No path found From what i understand, Maximum frequency is
It's expectable that the individual bits of a binary counter don't switch exactly at the same time. The effect is called delay skew. We see it e.g. in the transition from 0x43 to 0x44 in post #1. If post #1 shows the output of a simple binary counter, the glitches in the transition from 0xbf to 0xc0 are however not expectable. Similarly a synch
I want to read a 64bit input in 2 clock cycles. i.e. 32bit in 1 clock cycle and the remaining 32bits in 2nd clock cycle. the 32bit is divided into 8bit which serve as input for 4x1 Mux. So 32bit is being read using Mux. But how to read a whole value in 2 clock cycles can someone guide me with it please.
I'm designing a number exchange module, and so far I've been able to make it display on Seven Segment Display (S-S-D), like if I press 0 it shows 0... etc. I'm using 2 sets of 4-bits S-S-D (Common Anode). Now I want to do like: default states : 0000_0000 Now if I press 1 : 0000_0001 If I press 2 : 0000_0012[/
Hallo everyone, I m looking for a simple Code in verilog-A to build up an 3-bit Delta-Sigma Modulator. Is there any way to avoid the typically ADC/DAC blocks, for simplicity and behavioral modelingl? cheers, jo
154006 Observed signal floating in between signal. What could be went wrong? Please advice. -Kumar
Hi , simple logic analyzer project, with code - 8bit 200MHZ. Pof , Sof file included in zip file, you can directly progm Cylone 2 cheap board can
Regarding your question. Comparing VHDL and OpenCL as 2 languages is misleading. OpenCL is MUCH more then just a "Higher Level" language. It's a complete framework that describes communication mechanisms between hosts and devices. It's much better to compare HDL to HLS... Will I see any difference in speed? It depends. You can writ
Hi, I came across following generated code from vivado: (* EXAMPLE_SIMULATION = "1" *) (* SIM_SPEEDUP = "FALSE" *) some_ip some_ip_inst( .a(a), .b(b) ); I know to set parameter inside module we use this way: some_ip #( .EXAMPLE_SIMULATION (1), .SIM_SPEEDUP
I'm new to Synposys DC and I'm having trouble with timing analysis. Basically, I've got memories generated through TSMC's mc2-eu tool. Looking at the output .lib and simulation verilog, they seem to be reasonable blackbox units. However, when I instantiate them and define/constrain a clock, it appears as though Synopsys is only concerned with th
I am seeing what you have written and it includes none of your project files. So I find it difficult to answer your question. What if you remove the file in question from Modelsim project, add it back and then try recompiling? Generally in verilog, it is a good practice to include this compiler directive in the RTL files.[
I want to be able to run a simulation with a test vector located in a repository. The repository will be determined by users credentials. The repository will not necessarily be a relative path to where the script is executed from. I've read the following I
Hello all, The following code is task TSK_READ_FILE; integer scan_file; reg w_or_r; integer len; reg addr; reg data; integer i; begin while (!$feof(`ORIGIN.TSK_OPENR_FILE.data_file)) begin scan_file = $fscanf(`ORIGIN.TSK_OPENR_FILE.data_file, "%s %d
Hi, I am using ModelSim 18.1 for the simulation of my designs. Now the problem is I have some fairly obvious mistakes, and upon compile, ModelSim is skipping them and is not reporting the errors. For example, I have a verilog module like this: module a_module(a,b,c,d); I am instantiating this module like that: a_modu
hello everyone I know that tranif1(0) is bidirectional primitive and nmos is unidirectional primitive. In the aspect of simulation speed, is there a difference between nmos and tranif1 ? For example, nmos is faster than tranif1 because unidirectional primitive simulation calculation is half of bidirectional primitive. Is this right?
Sir I've interface 16*2 lcd with de2i-150 board but with same working code when uploaded on DE0_nano board its not showing output. Both board have same clock frequency of 50MHz. Here is my code: module lcd_test ( input clk, output reg lcd_rs, output reg lcd_rw, output reg lcd_e, output reg
You could consider using poly sources (vcvs) to create Vdd and the "switching input", a (say) 0-1V ramp at one terminal pair for the time varying aspect, a V=3.3 source multipled by the ramp is your rising Vdd and do the same scaling for a 0-Vdd pulse source through a second poly vcvs. Or you could go grab yourself a veriloga (or transistor level
I run the demo file "resistor.sp" from /usr/cad/hspice/cur/hspcie/demo/hspice/veriloga have this error: **error** call to epvaHDLinit failed. **error** Failed to read verilog-A file, see .valog file for details. **error** (resistor.sp:3) difficulty in reading input and the "resistor.valog":*pvaE*please invoke hspice
the number after a # delay (i.e. in your case assign #0.5 ack_d = ack) means #(timeunit) if your testbench has a directive `timescale 1ns/1ps or a timeunit 1ns statement then your # delay should be an integer in those units. SV allows you to specify the units in a # delay statement. So if you have timeunit 1ps and timeprecis
<-- Master <--- Block Diagram <-- Pin editor <-- Simulation Right now I have a master that was based off of Pedroni's i2c generic master from Finite State Machines, originally I had SDA <= 'Z' in the states I n