Search Engine

Verilog i2c

Add Question

1000 Threads found on Verilog i2c
Hello! I'm trying to implement a spread spectrum clock generator using a digitally controlled delay line in verilog. The basic idea is that I'm trying to modulate the period of my clock signal using some and_gates that each have a delay value assigned to them. The delay network just delays the signal, but it does not change the period of the
You have 78 terminals but only 6 defined in the subcircuit. I don't have enough knowledge about verilog/vhdl, however define buses width explicite in the module definition.
Maven Silicon is one of the best VLSI training institutes in Bangalore, India. We specialize in VLSI Design, Systemverilog, UVM, verilog & ASIC Verification courses. 100% placement assistance.
If you have tasks a, b, and c then if a takes 10, b task 2, and c takes 5 time units then the fork-join_any will exit when task b finishes (FYI a and c will still run to completion) and continue on to whatever follows the fork-join_any. In other words the first block that finishes causes the join to occur, hence the name join_any[
Create bits source where input value is decimal by verilog-A.
Hi, I have been working with the CCS811 for a while now. I have interfaced the sensor to the STM-32 L1072 chipset. While trying to read the hardware ID from the HW_ID register addressed at 0x20, I am getting a value as 0x80 instead of 0x81. I am using i2c for communication between the sensor and the microcontroller. Is there anything that I am miss
I am having unknown xx for req signal in a NoC verilog code implementation Please a single node within the Spidergon module spidergon_router #
I am trying to re-synthesize the benchmark circuit such that they only consist of 4-input gates, specifically ISCAS85 benchmarks available at instance, c432 circuit. Since, c432 circuit has several gates with over 4-inputs (up to 9 inputs), I want to reconstruct it with gates of maxi
Hello All, I am using Mikroc Pro Software, It has In built library. Controller: PIC18F46k80. I want to use 2 Masters and 1 Slave by using i2c communication. Can anybody please help me ? How to Start ? I have 1 Master & 1 Slave Code - Working Fine. Looking for 2 Master and 1 Slave :-( Thanks in Advance!!
ADS is not an Analog Design System. It is an Advanced Design System. Show me netlist. Simply you don?t include model definition which is described by verilog-A or ADSsim language.
I am looking for sample code for use with MPLAB and Code Configurator (MCC). I generated the i2c driver (i2c1_driver.c) using MCC, but I'd like to see an example of calling sequence to get basic master i2c working. Other than in the source code itself, where is the API usage for MCC-generated drivers typically described?
module my_XOR(output Out, input A, input B); wire x,y,inA,inB,not_inA,not_inB; and(x,inA,not_inB); and(y,not_inA,inB); not(not_inA,inA); not(not_inB,inB); or(Out,x,y); endmodule Do you see inA and inB being driven anywhere? I don't.
ieee.numeric_std.all; -- This is the official source for "unsigned" and "signed" types. Just use this. Monkeys on a ladder and whatnot. ieee.std_logic_arith.all -- This also defines "unsigned" and "signed" types. It wasn't from ieee, so people will look at its inclusion with murder-eyes. ieee.std_logic_unsigned.all -- This is the controversy pac
We can evaluate frequency characteristics of z-domain transfer function, H(z) by using verilog-A in Cadence Spectre. Assume H(z) = (1-z^-1)^3 = 1 -3*z^-1 +3*z^-2 -1*z^-3 Here we have three options as expression in verilog-A. (1) zi_nd(V(Input), {1, -3, 3, -1}, {1}, Tsample); (2) zi_zp(V(Input), {1,0, 1,0, 1,0}, {0,0}, Tsample); (3) zi_zd(V
Hi. I have been trying to simulate verilog ams with components coded in verilog, veriloga and analog (pdk given mos). I have done it and can see the wave forms but there is a problem, the or gate coded in verilog doesn't switch in output waveform window. rest all other gates are fine. 152975 the third waveform is suppo
I have this clarification i want to write application interface for nvram. The doubt is does the application needs to know the eeprom address where he is writing? How to implement such a logic where the same application is reading the data, i should read from the same location. Any sample code available?
Hi i implemented a vhdl code for checking results from TCS34725 there is no error in my code and i checked everywhere to correct and make it flawless but it does not work at all. I am not very good at i2c i just know the main logic behind it so i think my problem is connected to i2c but i dont know TCS34725 INTERFACE MODULE libr
Hi All, I am trying to interface the SHTW2 sensor from Sensirion with the nordic nrf52810 mcu. The Sensor uses i2c to communicate and nordic has its own version of i2c called TWI. From the datasheet of the sensor, The flow to get successful measurement is as follow: 152884 I am able to send the data over to the sensor
Hello, I am learning myself verilog (in which I haven't big expierience). During studying tutorial concerning verilog features I encountered some topics concerning "Switch-level" of circuit description. This is level of description in one can use transistors switches and capacitors. I was a bit surprised because in my previous expierience with V
Hello All, I am working with mikroc Pro licence version. I am using pic46k80 mikroc Controller. I received 1 frame that is 8 bytes frame from CAN, Received at my controller side. I want to send that 1 frame to another Controller through i2c. How to do ? Please help me. In library they given like; void main(){ ANSEL = 0;