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I made a verilog code for an up counter. I synthesized it in cadence genus tool by setting the clock frequency 30 MHz. After that I made a layout in Cadence Innovus tool for the same. Now my question is, how to find at what frequency my up counter ASIC will work? In FPGA the same verilog code was working at a clock rate of 20 MHz.
I have to generate a two different sine wave(1st sine wave normal sine wave which is generate from 0 degree and 2nd one phase shifted sine wave ) using verilog, and on google, I found something related to it but somehow I didn't understand. So, could anyone explain to me the logic behind this code? modul
I have written a verilog code of a counter, and I have done the synthesis of that counter code using Cadence Genus tool. Now I want to calculate the power. For that I have used the command report power and got the leakage power, dynamic power, mainly total power consumed what I actually want. Now my question is whether this power is related to any
Hi All, While doing GLS I observed there are $setuphold instead of $setup or $hold. Can anyone please explain me why we are taking $setuphold and how are we exactly interpets which violation is this (like setup or hold ) .What is the use of negative timing checks. Also while we are running GLS for MIN corner do we see se
Hi all, I I am using compiler CCS (v5.008) and MCU PIC18F46k22(has 2 MSSP module) , to display text in P10-DMD using MSSP2 module of the MCU. ---My target to use MSSP1 for hardware i2c (for RTC clock) and MSSP2 for hardware SPI (to display clock data in DMD).----- For that, FIRST going to setup Hardware SPI for DMD with MSSP2 Module,
Hi, i am trying to communicate with ACS71020 using i2c communication Basically i2c need Slave address. I want to know default slave address for the ACS71020KMABTR-090B3-i2c. In datasheet also not mentioned about default slave address.
If you get this kind of error, please check the input "read verilog file". You might have mistakenly put the pre-synthesized netlist and not the gate level netlist generated from design compiler
Looks to me like all the data is right justified and there is nothing being done to set the fixed point to a scaling factor of either 2**-4 or 2**-8 (comment does not match parameter). As calculations are right justified a 6.56 will be truncated to 6, so it makes sense what you are seeing. You should do some reading on Q formats (i.e. fixed point
Hello, i have approximately 32 Linux servers with 115200 baud serial console and i would like to connect all of them to single ESP32. While keeping things relatively scalable. I know that first i have to convert the serial level to TTL using MAX232. Then i have to somehow manage all that lines. Currently i am using raspberry PI with lots of US
Good evening to all There are so many document's available on the internet for i2c communication and I have spend hard time to understand i2c software protocol I am not looking for any code. I want to understand how does it work so I made one flow chart that explain my understanding I have attached PDF file and I am looking one guide
I have formally verified a round-robin arbiter code Could anyone advise about the various methods of minimizing the combinational delay tcomb penalty mentioned at the end of section 2.3 of Efficient microarchitecture for network-on-chip routers ? [B
Hello all, I am trying to figure out how often I can get new data from the NPA 201 sensor. In other words what is the Output Data Rate? I cannot seem to find it on the data sheet. All I can find is the maximum clock frequency for i2c. Link below for data sheet:
Hi Guys Can you please suggest a good verilog or vhdl book on implementation of optimised mathematical functions such as convolution, matrix multiplication etc... (or any other resource) Thanks very much
I want to write a code for a system which detects the absence of AC signal ,received after the digital filter (sampled @ 200khz). My ideas 1. level detector - If level is zero - no ac signal.(I liked it the most but struggling to come up with logic:bang:) 2. Continuously measure frequency of signal,but would need to increment counter for 1 sec
Hello, Can anyone help me to know that is it possible to implement any ADC on FPGA board by using verilog code? Or should i have to go through circuitry, and here i am not talking about implementation of onboard ADC or some external readymade ADC .
is there tool or method to convert netlist to rtl or structural code to behavioral code?
For doing this, I am using a current sensor that gives me current data(ADC conversion time-532 μs) in continuous conversion mode over i2c(400kHz) and I am using a Raspberry Pi Zero-W to store this data locally. I want to connect the maximum number of sensors on one RPI Zero-W, using bit-banging on different RPI pins, I want to know what is the
You need to think what this means: (9 downto ((64-conv_integer(divide))*10) Let start to see what happens if Divide = 64 you get the range (9 downto 0). If divide > 64 on the RHS you get 10 or more. (9 downto 10) Is a range with 0 length (a null range). This is prefectly legal in VHDL, and illegal in verilog. It returns an array with length 0.
I am thinking(in fact worried about) a topic that I have no answer for. That's why, I am posting here, and inviting international intelligentsia to come and share views. First my background: I am an ASIC designer who has just started my career in ASIC design industry. I am doing codes in verilog and trying to learn to verify them using Systemver
Hello! Does someone have any "step by step" course for STM32F429I-DISCO devboard? Regards Chris