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111 Threads found on edaboard.com: Verilog Learning
Hello team, I am a beginner learning to use verilog coding to measure power on Xilinx-FPGA. Custom-built circuit. IDE-- Xilinx ISE 14.7 I want to check if my AES encryption and decryption design works on an FPGA (with the highest switching activity so as to compare the estimated and measured values). The code below is just the TOP MODULE.
how to make simple led blink program in it? which programming language does it support? I think you must read and understand the basics first. (Although this is a Xilinx based tutorial, but can also be applied for Altera d
Hey new to the forum and i need help with a project i have de2 boards and i need to have one board encode a message and the other board decode it and display it on a the 7 seg leds we have the encode/decode code but not sure how to get them to talk
Maybe you should work on learning how to use a search engine. Try "verilog generate example" as the search terms. Or better yet find an online tutorial for verilog as generate is a typical tutorial topic.
Hi, I'm learning verilog and looking to understand intra assignment delays. I read some books and I think I have the basics covered. I was looking online for some questions and came across this which I cant seem to understand: Q: Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not i
Here is a FREE course that teaches basics of SOC Verification and Systemverilog language which includes a project as well. Try this out if that helps Looks interesting. Thanks for the tip. I take it you are the author of that course?
Hello all, I am looking to start learning embedded linux on my own. what and all requirements and boards do I require ? I have some fair amount of experience in FPGA design and implentation using verilog and VHDL but have no clue what C, Linux and embedded designs are all about. Please suggest me where to start from. I have a limited
Thats a very old part. I dont think ABEL will be much use to you in the future. You're better off learning VHDL or verilog if you want a Job.
when i am trying to link the three modules i am getting it compiled successfully but i am not getting the output of pid correctly... So your next task is learning how to debug verilog code. Did you already hear the terms simulator and testbench?
I have already working matlab codes for both detection and recognition. the problem is i don't know where to start in implementing it to fpga. i know little of verilog but i can learn fast. can somebody help?:?: thanks in advance.
usage of verilog and vhdl is more than other HDLs. learning of verilog is simple because it has c syntax. both of them are standardized by IEEE.
I'm trying to code my algorithm in behavioral modelling in verilog code. the following is my code module fpadd(p,a,b,su1,su2); input p,a,b; output reg su1,su2; wire c1,c2; wire v1,t1,t2,u; wire v2,w1,w2; integer i; parameter s=1; initial begin for(i=0;i<256;i=i+1) begin if(b) u=b;
Hi, I am new to Verification and I learnt Verification using System verilog. I am interested in learning OVM/UVM methodology based verification. Which is the best way to learn OVM/UVM? Should I attend any courses or can I learn by reading some manuals or text books? Please help me. Thanks. SK
Hi :) I've started learning verilog HDL for a while. Now, I'm studying gate level design. I wrote a module which ran normally in its test bench but when I further used it in another module something went wrong. The wrong thing is that I have a nand gate (in a module)whose inputs are {0 , 0} and its output is x. How come ?! Thanks in advance.
Hi i am new to verilog. But i know the basics. Any materials or links for learning FSM modelling and DDS? Hi arishsu, Refer this link, For further you can read the some digital
Is there some systemverilog step by step tutorial with some practical example?
Hi, I have started learning about verilog. To simulate the program, i need the simulation software. I found Icaris verilog is an open source software. I can't find the download page in their webpage. Please help. Thanks in advance :)
You can have that person start by teaching Systemverilog is one word, not two.
Hi - I am very new to verilog and am just learning the basics. I am trying to implement a slightly strange FIFO. I finished coding it, and created a test fixture for it. I tried simulating the test fixture in ISim and nothing seems to happen - I believe ISim is locking up. I have other simulations that run just fine - but this one just won't run. S
first of all, I suggest learning about digital logic and then start learning verilog or VHDL.
What are they trying to teach engineering students!? So many of the students learning verilog seem to use antiquated syntax and everything is built up of low level gates and master-slave flip flop designs. :-( I saw simple examples like this in the various verilog books I own when I picked up verilog to do my work, but I've (...)
In verilog, all static threads are started at time 0 from initial or always constructs. A thread may be split up by a fork/join constructs. If you count up the number of initial and always constructs , plus the number of statements inside all your fork/join constructs, you can determine exactly the total number of threads there will b
Hi all, I am learning verilog and this is a module used for read a character: module file_read() parameter EOF = -1; integer file_handle,error,indx; reg signed wide_char; reg mem; reg err_str; initial begin indx=0; file_handle = $fopen(?text.txt?,?r?); error = $ferror(file_handle,err_str);
Hello I am just getting into the Lattice Dimanod with MachXo2 stuff. I am also learning verilog at the same time. So far, I have managed to make counters and other interesting stuff. Now, for a real project, I need to load a heap of data into the pld via some sort of bus. I could use the SPI bus peripheral but just to get started, I would li
Dear Friends, Kindly, I just started the verilog learning to implement my OFDM system. As a first step, I need to implement a simple QAM Transmitter and receiver as a start point for me. I do not know how to send data to the system from my pc and how to collect it at the pc again from the FPGA board!! Would somebody advise me please? I need a
Hi, Im learning verilog by example from Chu's book.. so have a few basic questions.. this code is for a simple counter: module univ-bin-counter #(parameter N=8) ( input wire clk, reset, input wire syn-clr , load, en, up, input wire d, output wire max-tick, min-tick, output wire q )
The full name is verilog HDL HDL, stands for hardware description language. Always remember it describes something (unlike C or any other programming language). Therefore, before you get into learning to describe hardware I strongly suggest that you understand how that hardware works. By hardware I mean digital component
I dont knwo if there is any "C for FPGA" but i would not go on that way. HDLs follow a different logic than a software programming language. Try learning verilog or VHDL. I belive is the best way to start. Cya
Hi..... I am now learning place & route in SoC Encounter version 8.1. As far as i know to run/practice i should have 1.a verilog netlist(*.v) 2.a technology file (*.lib) 3.a LEF file for the library(*.lef) and 4.a script file(*.conf). But except verilog netlist i don't have any of the above. Could anyone please send some files (...)
VHDL / FPGA /ETHERNET project VHDL - layers of a standard TCP/IP stack VHDL / specman / with scripts log files and waves specman eRM- simple UART, tested with ncsim VHDL, verilog, design, verification, scripts, ...
Try out ISA - India Semiconductor Association .. you will get list of core electronics companies in india ... Core companies would obviously look for strong basics ... work on digital , analog , network analysis ... Learn "verilog" , it would definitely help you ... Get hands on experience on some simulation tools lik
And Micron's verilog model for that memory can be found here. Its under the Sim Models tab. Perhaps reverse engineering their model will help you develop yours. I have to say that you have quite a learning curve ahead of
Hi all, I've just begun learning verilog-AMS language and my first concern is which software tool to use in Synopsys environment. Please advice. Thanks in advance.
I started learning verilog and FPGA a few weeks ago and I have used a verilog script that does a Sobel edge detection by running it on a video stream coming from a camera attached to my development board. The code worked fine as I can see the edges being picked up on the VGA display. I didn't simulate it before-hand because I found these (...)
OK, I understand the parallel nature now. But is there a limit to that 'parallelism'? - Suppose I had two arrays of 2000 values each. Will that calculation depend on the size of the FPGA elements? - Suppose I want to do another calculation on the sum reg after the 'sum of products' operation has finished. If calculations ha
Apart from verilog,try to learn some HVL as well like system verilog. Now a days most of the people use SV for verification.Since you already know C++ so you should not be having any issues with OOPs concepts of SV . For learning it you should be readinf from LRM(IEEE 1800-2009) or can refer System verilog for Verification (...)
Now why would I do that? Is there any other way to solve the issue? It's simply required. In VHDL, a register is generated automatically, you don't have the option to specify different signal types. If you prefer learning verilog by try and error, which is basically possible, then you should try to get a sense for the compiler er
Hello, Im new to verilog and am learning it myself.. What im trying to do is to create a simple system, a part of it is an irq timer module... its supposed to generate a pulse determined by a parameter and each pulse should last for 4 clock cycles. here is what i worte (its my first verilog module) module timer( input clock,
Hello, Does anybody have any information to help me to start writing my codes? I am quite new on OFDM and verilog and don't know from where I should start. Thanks so much, Mehrnoosh
Sometimes verilog's loose typing makes me a little sad. :-( Every now and then you will make a typo, which gets silently ignored by the tools. Only your design will not work. Joy. I know one obvious answer is: "Well now, you should VHDL! VHDL is awesome, strict typing and stuff!". No doubt, but this would also mean a new learning curve + as with
This link may help you if you need an example of synthesis, using XILINX XST, and than simulate the post NGD net-list: "The following describes the synthesis of the VHDL IP stack, using xilinx XST...." VHDL, verilog, design, verification, scripts, ...
You may want to take a look on script, which I wrote lately. A sort by multiple fields: PERL script... VHDL, verilog, design, verification, scripts, ...
hello every body i should write a verilog code for fft but i hardly know verilog syntax, i am very tenderfoot in it i need an emergency help for at least learning the concept of its algorithm so i would be glad if some body can guide me with a lecture which explains the algorithm i wrote fft code in C++ before, but as i understood this (...)
hi everyone. I am learning system verilog from a website individually. Hence I need a simulator to run the programs. Could anyone help me. Thank You.
This is a nice book that explains VHDL and verilog @ z same time -- Amr Ali
Hi, I am design a ΣΔ fractional- frequency synthesizer, and I find a verilog code for the digitao sigma-delta modulator, which is a single-loop multi-bits quantizer. The output is 5bit and the input is 22Bits. Its structure and the verilog code are shown below. But when I simulate this verilog code, the result is not right. The (...)
I have read a book about verilog, I am finding some interns in US. So do I need to read books about system verilog? If yes, can you guys recommend some entry level books for me? Thanks!!~
Hi, I've been learning the basics (very basic) of DSP and I wanted to try to implement things in verilog. Histograms DAC->ADC etc. How does one go about doing this on an FPGA? I have the Spartan 3E starter kit. Not an FPGA built specifically for DSP, but should be enough to get something going.
Hi to everybody! I've just begun learning verilog-AMS language, and my first concern is the possibility to use the created file in AMS Simulator (in Cadence SPB 16.01). It's not very clear to me how I can implement a verilogams file in a model; normally I use Design Entry HDL, which theoretically gives the possibility to add parts (...)
Hi, FPGA programming is done either in vhdl or verilog(as of my knowledge get good knowledge in these hardware languages.There are many books,or you can read the data sheet of the particular FPGA you want to work on and go ahead. All the best!