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112 Threads found on Verilog Mode
Hi all, I am trying to do function verification using System verilog. I have DUT developed in verilog. The DUT is very complex. I would like to run multiple test on this DUT, from batch mode. The compilation and elaboration of the DUT takes long time in the whole simulation process. So I am wondering is there a way I can compile, (...)
Hi, I am an EE uni student and have been currently working with verilog on the Basys3 for the past few months. I would like to program the FPGA to be able to take input from my USB mouse i.e. clicking on the left/right mouse buttons to trigger output such as LED or changing reg values. So far, I only know that constraints have to be set to the C
Here is the code I created module clk_24hours ( output reghr_time, output regmin_time, output buzzer_mode, input clk, input hr_adv, input min_adv, input mode, input set_time); input alarm_is_set; output hr_selected, min_selected, ahr_selected, amin_selected; input [1:0
Hi, I am designing a hybrid content addressable memory (CAM) using cadence and I need to build a verilog-A block to switch modes. In the read mode, I need to pre-charge some nodes then make them floating. I tried different verilog-a lines but the code always fails. For example, I tried using the following line that I (...)
I am running OVM env together with some behavior model descripted in verilog. But seems it is never working.... assign #0.2ns A = B; But below is OK (changed to always) always @ * A <= #0.2ns B; Since another env without OVM is OK, so i doubt it is related with OVM or some delay mode setting.
Hi All, What is the Best Editor for verilog Code Navigation? Thank you!
FPGA simulation will be done in an RTL simulator like modelsim, NCsim or ActiveHDL. You may be able to do mixed mode designs using VHDL/verilog AMS, but this requires you get hold of or write the AMS models for your circuit.
Hi, I'm running a mixed mode design that is using verilog for digital and spice netlist for analog. The tool is using ncverilog. I'm wondering that I can't see any response from the analog design on the waveform that is in a fsdb file. Is is a problem on fsdb dump? Suppose, the dump systemtask $fsdbdump is the same as that using in (...)
Hello, I need help with one program, which i am trying to make for Altera DE2, I am just basic programmer in verilog and I would be really happy if you'll help me. My problem is so I don't know how to make so when I push button for >= MAX_TIME so I need set diods on 18'b000000000000000000 and so on fourth mode I need to make cyclic turning on diod
it is a simple half adder program. program is like this half adder module add(sum,cout,a,b ); input a,b; output sum,cout; xor a1(sum,a,b); and a2(cout,a,b); endmodule add.ucf is: NET "a" LOC = L13; NET "b" LOC = L14; NET "cout" LOC = E12; NET "sum" LOC = F12; [/synta
Hi, I am doing some mixed-mode (VHDL + verilog) simulation. My testbench is in VHDL and the I have two other modules which are written in verilog in two separate files. I have also generated separate SDF files for each of them. I followed the following procedure to run the testbench: 1) compile each verilog fi
Hello all, Problem is , when trying to download my verilog code to platform flash prom (of xilinx ) the program (ISE Design suite) said that the programming is done and all is okey, like this picture 95030 on Master Serial mode . now i should look at my kit and find that the done led lights (as usual ) but it's
You can't connect 'reg' with inout port in verilog. This is done because 'reg' can't be driven any way except procedural assignment. If you really need connect this 'reg' to inout (ex., inout will be always in 'input' mode), you can use something like this: ... reg in_reg; wire in_wire; assign in_wire = in_reg; ... .inout_port(in_wire), ...
Hi people I have been trying to implement the following code which is a current mode comparator into mentor graphics ADMS tool; I have been receiving the following error: Analog DC computation aborted : no DC convergence found in this design Is there any problem with my code ? The schematic is also attached. `include "disciplines.h" module
Hi This time again I am in need of your valuable technical tips I am trying to interface Micron's SDRAM MT48LC4M32B2 with the spartan-3E XC3S1200FGG320. I have gone through the datasheets having multiple timings. Can anyone help me with some sample VHDL / verilog code to interface it in page mode or can share your experience to boost
Use only one initial block. Secondly does modelSim 10.1d PE support system verilog?
i have a verilog code for memory .I want to check read and write operation in it . i gave address and data. but i want to load memory register in it (before read and write ). probelem is mode reg is declared as register (not as any input or in what form i shud give it in testbench. i cant directly give its value since it is not a input o
Hi, I am trying to instantiate a verilog based IP into a vhdl top file. There are around 15 I/Os in the verilog based IP. Out of these signals one signal in particular is VDD. When i try to instantiate the IP in VHDL top file, the ncelab gives an error as follows "ncelab: *E,MXINDR: VHDL port of mode IN, (...)
This script is used for automatically generating verilog instance from the file. When you type the given hot-key, instance will be copied to system clipboard, and display or not by its working mode. Once your file can access syntax check, this plunin will work, or there must be a bug. It's encouraged to share it with me and all other peopl
Hi All, I have started my career as VLSI Design Engineer and i am trying hard to learn certain things in synthesis and STA. I have created an I2C Slave with the intention that it should support std, fast and HS mode. I have completed coding it in verilog HDL and have made sanity verification. Now on coming to synthesis part, i went through the S