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27 Threads found on Verilog Programs
hi i am designing an alu using verilog alu ,in division, how can i handle divide by zero condition. in this $display("error"); is not allowed. can i do anything with high impedence state 'z'. or do i need to use any flags i hardware. plz help me im confused internet they are saying that u need to do it in hard
Hello friends, i want the verilog code for square root of 32 bit number. i tried a lot with many programs but those are working for small values of integer numbers only. i have tried to use ip core too but the delay has been increased when i use ip core. i'm using xilinx 10.1 with virtex-4 as my target device. i'm not able to find
Hey I have designed a median filter in FPGA using verilog. I have given the input in this programs using readmemh command in test bench. The problem is that For my input A,B,C,if i want to assign A=first value B=3rd value n C = 7th its giving xxxxx in output thus its unable to read unsequential data from my input file . Please Help Regards
Hello, I am having the following error while trying to compile my SV codes. I'm getting this error for my verification codes. Error- Syntax error Following verilog source has syntax error : Class declaration outside programs requires "-sverilog -ntb_opts dtm" switch "../verification/", 4: token is ';' cl
Good explanation from this book: But you need to convert the VHDL code to verilog. Thanks.
Hello, I m working on a Altera DE2-70 board, and i need simple vhdl/verilog programs to make use of all the resources in the system. The available resources are ? 2-Mbyte SSRAM ? Two 32-Mbyte SDRAM ? 8-Mbyte Flash memory ? SD Card socket ? 4 pushbutton switches ? 18 toggle switches ? 18 red user LEDs ? 9 green user LEDs ? 50-MHz oscil
Do you have the verilog code? If so where can i find that out? Suppose you have the verilog code. First step is understand it a little bit Second is simulate it with some instructions to see if it correctly simulates the instructions Third step is to write one or more programs which consists of multiple instructions to see if it works (...)
Hi guys I have got this problem for a month ,but i don't know how to finish it ? So will you please send me the programs to me ? So I can have a better knowledge of IIR Thank you
any one know about the use primitives in vrilog hdl. How to implement in program. i need help.:? pls give me one example. reply fast.
hay every one, i am new to verilog, tried to make some small programs like clock etc. now i want to design an ADC chip as one of my course projects. actually i want to design a chip that works as and ADC if the mode pin is high and DAC if its low. plz gude me out, and suggest me that if its a nice project or not? and will a person having little ver
online links for vcs manual and installation in linux ..Vcs for system verilog simulation
hi everyone. I am learning system verilog from a website individually. Hence I need a simulator to run the programs. Could anyone help me. Thank You.
You can simulate your design in Altera Quartus using built-in simulator or Modelsim. But that is mainly intended for logic simulation, not the final design which is tied to baord. The only thing is that you'll have to create the simulation test bench that will simualte the inputs to your verilog circuit.
can anybody help me this...i need programs which are synthesizable in xilinx ...urgently for T.E project Hi, You can try basic codes like counters,shift registers,flip-flops.These codes are synthesizable in xilinx.For that you can browse these codes in internet either in VHDL or verilog. Cheers,
Lets say I have two programs in verilog, one the LUT and the other some logic circuit with a clock. Lets say in that circuit 'a', a1 is an output. a1 is input to the LUT and the output of the LUT is the new clock value for 'a'(clock is an input to 'a'). eg: if a1=2'b00, the LUT changes the clock to 125 khz from 1 MHz. How could I code this? (jus
never heard.... only heard verilog/VHDL can burn into IC.
I have written code for an ALU in verilog and have simulated using Xilinx.Now I want to simulate it using Cadence tools and also calculate the power consumed by the design. Do I need to modify my programs for NCLaunch and also can anyone tell me how to calculate power using Cadence tools?
this is one of my favorites :D that's for VHDL .... for verilog, there's the book of Morris Mano (digital design) it makes you learn digital circuits by implementing them in HDL (verilog used here) it's on the forum and it's a great book
Hi all, I am very new to verification.I know these are very basic terms. can anyone tell the difference between these terms with some simple verilog programs if possible. Thanks
can any one help me to develop code to convert a floating point number to binary and writing code in verilog. can u sujjest some sites or material or can give any code for that pls help. i have to develop a FIr filter in verilog and in that i have a need to convert floating point filter coeffecients to binary and hv to develop coding in (...)