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79 Threads found on edaboard.com: Verilog Signed
3-bits cannot represent numbers like 1.7 etc. all possible numbers in a fx2.3 (positive only - 2 integer and 3 total bits, i.e. 2 integer and 1 fractional bit) representation: 000 - 0.0 001 - 0.5 010 - 1.0 011 - 1.5 100 - 2.0 101 - 2.5 110 - 3.0 111 - 3.5 as you can see the bit width of 3 is limiting the values you can re
hello i am doing a verilog project that design a FIR filter. i generate sin & cos waves with cordic algorithm and apply it to FIR fiter. i am not sure about response. this is the code of fir filter: module FIR_filter(input signed x, input clk, output reg signed yn); reg signed xn; wire
I need some help getting started with writing the following two sort file. Can someone help? (a) Write a module sortEight, which accepts eight signed values and returns eight signed values sorted from least to greatest. You should submit one file for this problem called ?sortEight.sv?. Any additional modules should be inc
Hello everyone, I am trying to design 32 bit binary signed digit adder but I am facing issue while writing code for signed number. i.e for example if we take number let it be X=10-111 , then I want to represent X as (X+ = 10011 and X-= 11011) then how implement it in verilog. please help me.
Apart from Babylonian method (cannot use this) what other algorithms exist that can be implemented in verilog. Requirement is to calculate rms of a series of 32bit signed numbers
HI, I am new to system verilog and was trying to simulate the following simple program but am not able to understand how the output is beign generated: module test (); initial begin byte XYZ; foreach(XYZ) XYZ=i*100+j; foreach (XYZ) begin $write("%d:",i); f
Hi, I'm trying to code a signed multiplier, and I used 'signed' for the ports and wire, but when I run (ModelSim) simulation to check it, it doesn't work for me. Below is the code and the simple testbench. The numbers are the most positive (0xFF) * most negative (0x2000). In simulation, I get 0x1FE000, which is not the correct answer. Any idea
Then you need to read a book on VHDL (or verilog)... c <= a*b;
Hi, I read the following about verilog expression: Example 4-1 shows two ways to write the expression ?minus 12 divided by 3.? Note that -12 and -d12 both evaluate to the same bit pattern, but in an expression -d12 loses its identity as a signed, negative number. 108105 I do not know what [
You have to be very careful when using signed arithmetic in verilog and System verilog. Unless you really understand the way the language treats signed values, and especially the way it treats combinations of signed and unsigned values, you can find many ways to hang yourself. In your (...)
I have written a verilog file that implements some arithmetic operations, I defined my signals as wire signed or reg signed. when I simulate that on isim simulator it does the operation as specified, with signed arithmetic. but when I simulate the same file in modelsim it behaves as if the signals are (...)
I have to multiply two fractional numbers of 42 bits in verilog. I am using the fixed point (Q12.30). Now my result is wrong. part of my code: module my_name (out,Clk); input Clk; output reg signed out; //(Q24.60) reg signed in1; //(Q12.30) reg signed in2; //(Q12.30) alway
Hello All, I would like to make a signed multiplied on verilog, using an Spartan-6. Spartan-6 has the DSP48A1 multiplier, that is able to make a pre-sum, and a post-sum. Meaning I can write the following code: wire A, B, C, D; wire MUL = ((A + B) * C) + D; And the ISE will synthesize a DSP48A1 multiplier.
I have a hard time believing that. How did you come to that conclusion? - - - Updated - - - Also, you did notice the difference between a vector and a number, right? I just gave you a single 8-bit signed number. No need to add the extra confusion of a vector of signed numbers if the problem of the day is "H
Assuming the file in like : .1 .12 .15 .2 .26 .3 and so on write code like this integer in,i,out; real data; initial begin in = $fopen("input.txt,"rb"); out = $fopen("output","w"); if(!in) $display("File Open Error!"); if(!out) $display("File Open Error!"); i = $fscanf(in,"%f",data); i
Hi all, as fasr as I know verilog cannot read negative numbers, but I have no idea of writing test bench from VHDL and since time constraint I am getting more and more confused as I open each link via google for VHDL read file... I have data with both negative and positive integer format and am unable to read the data. I did previously s
Hi I have designed a 8-bit counter using verilog. I simulated it using modelsim. counter is performing it's function correctly till the total event at the output reaches 127 (i.e after counting 127 clock cycles) but after 127 I am getting a value of -128, then -127,126,-125 and so on for each additional clock cycle. why it is going to -128, why
verilog_ project 36-Efficient VLSI Implementation of 2n Scaling of signed Integer in RNS .pdf 2nbit csa with eac -verilog code please carry save adder (csa) end around carry(eac) ;; charantej.peteti@gmail.com below i posted my project - i have to solve that
i need a verilog code for 8bit signed carry look ahead adder..... i dont know how to convert the following code... help me soon....:-( module cla(sum,c_8,a,b,c0); input a,b; input c0; outputsum; output c_8; wire p0,p1,p2,p3,p4,p5,p6,p7,g0,g1,g2,g3,g4,g5,g6,g7; wire c1,c2,c3,c4,c5,c6,c7,c8; assign p0=a^b, p1=a^b[
i need to design a multiplier unit.. design idea: only binary inputs representation signed representation..can provide a sign bit input.. ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program