Search Engine

Verilog Transfer

Add Question

43 Threads found on Verilog Transfer
Hi, I am designing a discrete time integrator with transfer function = 1/(1-Z^-1) using model writer of the cadence virtuoso, below is the verilogA code of the integrator. But I am getting a gain of more than 1000 in the output, when applying an input signal of 900 uV (p-p). I added the screenshot of the schematic as well as the transient outpu
Hello, How do I transfer a va file into ADS? I want to transfer a tunnel fet verilog a file into ADS.
I am designing a noise shaping block as seen here the Simulink file is also attached. I accomplished it in Simulink and want to transfer it to verilog. However, I faced with very robust miscalculations. The output in verilog goes unstable . I have no idea how to solve it. If possible could you please your comments and idea about the (...)
I want it in system verilog Write separate task for each read and write. (and also for each master/slave) - I need to drive the htrans signal. (not just sample) - If I have initiated a transfer. I need to wait for relevant signal to get asserted. (you cannot just check for ready and exit the task, i.e. if master initiated a write transfer (...)
Actually for asychronous fifo if i want to compare the expected result with the produced result i need a queue . so i want to transfer the first input of my data_in into queue and later i compare the data_out and queue. so that it become first checker. i want a code for that. system verilog or if possible i want it in verilog
I want to implement PID controller in verilog? How to calculate proportional, integral and differentiation gains and what will be the approach for this??
Hi all! can u help me to make a verilog code on designing synchronizing FIFO for data transfer from CLK0 to CLK1 using handshaking protocols and dual port SRAM (64x4)? CLK 0 = 50 MHz CLK 1 = 15 Mhz with the following inputs and outputs: Read Process: input rd_clk; input rd_rst; input rd_en; output rd_dat
Hi, Register-transfer-level (RTL) abstraction is used in hardware description languages (HDLs) like verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design. RTL is used in the logic des
$fscanf is not synthesizable. It is used for testbenches or behavioural models. If you want to transfer data from a PC , you will have to create a hardware interface in the FPGA that can pull data from the PC and software in the PC to send the data to the FPGA. IIRC the Spartan boards have a USB/UART chip that you can use. You would design a UAR
So the circuit actually can't determine if one of its inputs is in the Z state. Right. Z is only synthesizable on outputs. X is supported for definition of don't care. Although not necessarily implemented by all synthesis tools, IEEE 1364.1-2002 IEEE Standard for verilog Register transfer Level Synthesis gives a general id
The stuff in the Always block is RTL code. The stuff in the Initial block is not RTL Code. But both is verilog Code. Yes and yes. So yes. ;-)
Hi,there. When modelling the opamp by verilog A/MS, people usually use Laplace transform filters to approximate the small signal behaviors like the code fragment below: V(out) <+ laplace_zp(V(in), '{-1,0}, '{-1,-1,-1,1}); But I dont know the exactly meaning of the laplace transform filters function. From the verilog AMS LRMʌ
This is an artifact of the way current synthesis tools want to see DFF modeled as a single process. Artifact is a good word for this contradiction in terms - using the edge keyword for a level sensitive event. But the latest with IEEE 1364.1 Standard for verilog Register transfer Level Synthesis, the syntax has been accept
1. RTL is designs in VHDL or verilog. Synthesized netlist is produced when the RTL designs is translated to logic/standard cells according to certain technology. Both have similar functionality but different forms. Thanks
I want to write a verilog code for transferring data from one memory to another in which i have to define the to memories first and then transfer the data (the size of both memories is same). please help me with a verilog program.
RTL is register transfer level, it is the VHDL/verilog code of your design. Thanks.
HI The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 " for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0 thank you !
Hello, I need to write a script which will transfer specific module/s in the verilog design from one place in the hierarchy into another. The problem occurs when I face design with ifdef and generate->case/if statements. I know this could be done, but this is a hard work, so I want to be sure that I won't reinvent the wheel. Maybe someone
What is baud rate. I don't understand it completely. All i know is, it act to slow down the clock for the data transfer or am i wrong about this. How can write its verilog code for the baud rate generator.
I have several common issues: (1) who know how to send data from FPGA to PC usb port? I found a usb ip core, but i think it's not easy to use. (2) did any of you try convert matlab code to verilog code? is it good or not? (3) can microblaze deal with float point calculation? It's very difficult to solve math problems in fpga, is there any good