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Verilog Virtuoso

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71 Threads found on Verilog Virtuoso
Hello all, I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors: Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSYS_UNCONNECTED__0". Error: (DB-270004): Illegal bus reference - Can't tap "
I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command: -phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple
the errors gone .Show us logfile of Cadence Spectre. If you would like to use "" without having two verilog-A files, try the following. Make new file, "aho.scs". Content of "aho.scs" is following. simulator lang=spectre ahdl_include "/home/eslam/Desktop/IGFinFET_model/"[/cod
Hi, I have written a verilogA code for a track and hold circuit. I simulate it (by using the symbol view) and it runts properly. Is there a way that i can handle a circuit or work at least some layout from the code i have written? Is there really an analog circuit behind my code or is it just the code running ? Thanks
Hi, I have loaded a verilog file in Cadence virtuoso in which i implement an 8 to 3 an input i have an 8bus the code i used an array with 8 bits for input and 3 bit for output.I want to run a test in the schematic.How can i give an input with 8 values??
Build FIR filter model using verilog-A. You can find many examples in "rfLib" of Cadence dfII.
hi every one I try to run verilog-Xl from virtuoso but that massage appears SIMULATION OPTION WARNING: Invalid verilog executable verilog Please check existance and/or permissions and try again. Relative pathnames are relative to run directly. I googled it and I found I need to install ldv package but I aleardy have (...)
I want to use verilog.inpfiles.flattened from schematic which has some behavior view and has `include definition inside. The problem is that virtuoso flatten netlisting seems to fetch contents inside `include definition instead of just leave this `include on the netlist. That causes my netlist a mess and somtimes can not be used for simulation.
hi, I am new user of cadence incisive unified simulator. I want to run a mixed signal simulation. I am able to run a mixed signal simulation of a design consisting of a verilog module and an analog schematic module, when using cells only from analogLib in the schematic. The problem is when I use the cell from the foundry library there are errors in
Hi all, I am running a AMS simulation in Cadence virtuoso. My output from a block (in verilog code) is a bus of 19 bits. I want to write a verilogA code to write the bus data (at every negative edge of clock) in a text file. Can anyone help me with the code???
Hi. I'm trying to simulate an ideal MOSFET in verilog-ams. After the code been written, save it under a verilog-ams cell viewn in virtuoso, and them the symbol is automatically created. As soon as I instantiate the symbol in my Test Bench, when I try to run spectre (with verilog ams already defined) I get the following (...)
Hi all, I just start to learn verilog-a and want to create a voltage-controlled current source(vccs) in cadence virtuoso. I learned that cadence would check my syntax automatically and create the symbol if the code is OK. However, when I open a new cellview in verilog-a, I can't save the code, so I can't convert the code to symbol... (...)
The most well know suite is probably Cadence virtuoso. This will allow you to do verilog netlist, spice netlist, "graphical" schematic and layout. Most state of the art foundries "support" cadence natively. There are many other tools out there that are really good too, for example Synopsys, Mentor Graphics, Micromagic, just to mention some.
There is in CIW window menu Tools and there is NC-verilog. Run it and choose the correct schematic. You can generate verilog file there.
Maybe you can import VHDL/verilog netlist (synthesized by DC or other tools) directly into virtuoso environment. Then a new schematic will be generated and can be used to do further simulation in ADE. Regards,
Hi. I'm using Cadence virtuoso with verilog ams. I pretend to build a counter with a 9 bit word. How can I check the value of the counter? Regards.
Hi, I'm new to verilog and i'm trying to validate the theory behind a oscillator for TDC purporse. //verilog-AMS HDL for "ADPLL", "work_tb" "verilogams" `timescale 1ns/1ps `include "constants.vams" `include "disciplines.vams" module sgro (con1, vs1, vs2, vs3, vs4, vs5); input con1; output vs1, vs2, vs3, vs4, vs5; re
Hi all, how to change verilog's values from schematic window, like with regular transistors (button Q)? Maybe there are special functions. or is it possible ? thanks in advance. tags: verilog A, verilogA, verilog, Cadence virtuoso
Hi, there. I want to create a verilog netlist for a schematic (cadence virtuoso, version 6.1.5). From a tutorial I found online, it seems that I can do this by verilog-XL. The tutorial shows me that selecting Tools->Simulation->verilog-XL can invoke the "setup environment" window, but I can't find the (...)
Hi, I don't have much experience in such things, but maybe it'll be less boring if you try to use Stumuli option instead voltage sources, or (the best way I think) you have to create verilog-A block just for tests.