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63 Threads found on edaboard.com: Veriloga And Cadence
Does anyone has an example of transmission gate (or MOS switch) veriloga code? Please provide an example you have. I already tried this but does not work. module simple_switch(in, out, tp); input in, tp; output out; electricl in, out, tp; parameter real vth =0.4; real vout analog begin if (V(tp) >= vth) begin vout =
Hello guys, Does anyone have a verliga model for a ROM (any type)? I was curious to know how you programmed it! I am not sure if there is any general way for doing this. I would greatly appreciate it if you could share your thoughts on this matter. Thanks.
Hello all, I want to design a model of a MASH 1-1-1 ( 3rd order sigma delta modulator) in Verilog A. I am new to veriloga and i am having trouble designing it, especially the delays of the error cancellation network. Any help will be greatly appreciated. Thank you in advance
You might be able to modify a veriloga module to hold the verilog guts. Probably have to add stuff at the interfaces to get sane transition times, delays, and pin-impedance-dependence for good analog behavior.
Hi, I'm a new poster, please excuse me if I do something wrong. I'm trying to model a device in veriloga and then test to see if it works using cadence. The model is below: // veriloga for tech_support3, test, veriloga `include "constants.vams" `include "disciplines.vams" module test(p,n); (...)
Hi, I have written a veriloga code for a track and hold circuit. I simulate it (by using the symbol view) and it runts properly. Is there a way that i can handle a circuit or work at least some layout from the code i have written? Is there really an analog circuit behind my code or is it just the code running ? Thanks
Hello, I was trying to use veriloga to write a model file and simulate it in Virtuoso cadence. When I try to simulate i get following error Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid (...)
I can encrypt the "mymodule.va" file and create a new encrypted file called "mymodule.va.vap" in cadence Tools by the following. unix> ncprotect -extension vap -language vlog -autoprotect mymodule.va I have a question. How to unencrypt this "mymodule.va.vap" ?
hi I want to simulate the veriloga model of OTFT transistor but see this
I think this is best done in veriloga (which Spectre digests just fine, and cadence supports editing and view-switching). You will want to error-trap that denominator, and a poly- source / analogLib primitives kludge probably doesn't have much for that. I'd recommend to find a resistor (...)
Dear all, I have implemented stanford CNFET model in veriloga(no errors found) then made a symbol(no errors found). Then i wanted to use it in circuit(dc sweeping/transient analysis) to see whether the veriloga does what it is supposed to do. When i try to simulate gives me the following error: "ERROR: Netlister: unable to descend into any
Reference existing thread I am facing a similar problem. I want to model a cntfet in cadence using veriloga. I used the veriloga code ( ). I followed these steps to create the cntfet model- 1. I created a new veriloga cell v
Hi dick_freebird, Thanks for reply. I can edit CDF once I created cellview. But I am not able to create cell view. when I am trying to create cellview it shows syntax error in verilog code. Can u plz helpme ??? Yes, the cadence-spawned veriloga editor will automatically check syntax and you may have to save-as
You can do almost anything you can conceive, in veriloga and Spectre will digest it just fine; you have to create the veriloga view alongside the symbol and make sure that it is picked up by your switch / stop view list order (or by using Hierarchy Editor and config-view based simulation).
You should synthesize verilog file in rc-compiler and then import a new verilog file with physical gates into virtuoso. Thanks. But after synthesize how can i make symbol and link with my schematic. (how to call it in the virtuoso) Also, is there any way to verify the behavioral working in virtuoso
Hi jxyang1005 Do you try to run ADE XL and ADE GXL? You should try to run mixed signal mode as veriloga or verilgo drive schematic to see mmsim work. My setup work only ADE L and veriloga do not work
Hi I am new to using spectreVerilog simulator and doing some top level sims on an ADC in cadence 5 environment. I have some verilog, veriloga and schematic cellviews. I have just selected spectreVerilog and selected transient analysis. and on running I get the following error in the icfb (...)
I've never tried to sweep temperature, but I often use Parametric Analysis to step it and plot stuff. Perhaps the problem is in getting frequency as a scalar value. My version of Calculator has a freq function that can be used on transient simulation results. I have also used a veriloga "widget" to generate a voltage proportional to frequency. Ma
You might be better off with a veriloga source that reads tabular data (or has it embedded in the code). I've built these using a concatenation of header, "core" and tail using shell scripts to massage plain text, time voltage pairs at one per line, to make very long "digital" vectors. Since the header and tail don't change the (...)
hello All , I am trying to prove the matlab code via veriloga opamp model with ideal switches and capacitors on cadence, to prove the STF, NTF, OSR according to Schreier ,I need to do an impulse response check on my ADC, this simply means removing the Quantizer from the loop and with a veriloga model I (...)