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Veriloga And Simulator

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16 Threads found on Veriloga And Simulator
Do you want to vary by simulator variable, by circuit voltage, or what? I suggest you look at whether veriloga is supported by your HSPICE version and if so, scrounge for veriloga varactor code you can modify to suit (or, find a varactor model you like and just linearize or cal-map the C-V transfer (...)
You should synthesize verilog file in rc-compiler and then import a new verilog file with physical gates into virtuoso. Thanks. But after synthesize how can i make symbol and link with my schematic. (how to call it in the virtuoso) Also, is there any way to verify the behavioral working in virtuoso
Dear all, I want to simulate a netlist test.sp which includes a veriloga file by this line: .hdl "./" and I run the hspice like this: hspice test.sp -o test and the simulator just halts there and won't stop! No any errors and no any messages. I (...)
Hi I am new to using spectreVerilog simulator and doing some top level sims on an ADC in CADENCE 5 environment. I have some verilog, veriloga and schematic cellviews. I have just selected spectreVerilog and selected transient analysis. and on running I get the following error in the icfb (...)
Hi to all, I am designing one model in veriloga. My equation is like Qs_low1 = Charge_low(`alpha_1,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1); All H1,b1_1,bo_1,L1 are declared as real. It was showing the error at "," after H1, if i replace H1 wi
I got an error from Cadence on simulating a veriloga bench. Below is the message from the simulator. I googled and can't figure a clear clue out of it. Mixed information there. How can I get into ahdlcmi directory to see details? Any known solutions? - Neo (...)
I think veriloga is your friend. I've built things like veriloga widgets that watch one node for zero crossings and compute a "present frequency" and produce it as a voltage on a pin. I'm sure something similar for risetime would be trivial (although you want to stay away from nanovolts as this will be buried in (...)
i have a circuit constucted by veriloga symbols and mosfet. When i simulate it in hspiceD simulator , the system prompt "Netlist Error: Formatter method nlIncludeverilogaFile not defined." "Netlister: There were errors, no netlist was produced." ...uncuccessful. What should i do to solve the problem? Hope (...)
i want to modle a time variation resistor with noise power 4kTR,but I have no idea how to do. any one can help me? need your help
Hi, I am new to veriloga and looking for a veriloga simulator. Can anyone suggest a free simulator which I can use to do prelim. experiments. Any suggestions will be welcome :D. Thanks,
All model and instance parameters are described in module as instance parameters (e.g., parameter real W=...; ... parameter real U0=...; ) In Spectre 5.1.41 there's no option to mark out "instance parameters" (like "(* instance_parameter_list ’{parameterList} *)" in Spectre 6.2). Therefore all parameters are instance paramet
I am doing a top-down mixed-signal ASIC design. Now I have veriloga, functional(verilog code), schematic and config view for blocks. Do I have to use AMS designer to simulate with these views? I think Spectre simulator can handle the mixed signal simulation very well since there is no verilogams view in my (...)
Which is supported by spectra_verilog and which is supported by eldo_rms?
I need a version in linux that supports verilog and veriloga You can use the mixed-signal simulation flow by modeling the verilog in digital simulator and modeling the veriloga simulator. For example, ncsim+hsim or VCS+nanosim/hSPICE
How do I save data of the simulation result in cadence so I can export to matlab or excel? and where is wavescan in ADE? If the simulator supports verilog/veriloga, you may use verilog/veriloga module to sample the outputs and write to a text file. If you want to write the Analog Artist wave data to (...)
One of the best thing I found for PLL was spectreVerilog simulator included in cadence IC environment. But this is true only if you have complex PLL with large digital core. In such case you can replace analog components (VCO, PFD, Charge pump ....) with veriloga model, and use verilog model for digital cell. This will allow you to evaluate (...)

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