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19 Threads found on edaboard.com: Vhd Bit
Hello, I have a Vivado project with *.v & *.vhd files. When I double click a file through "project navigator" it's opened through Vivado's native text editor. Is it possible to to make the files open through Notepad ++ (or any other text editor) instead ?
hello. i want to store time as real in vhdl.how do i do it?for example delay:time:=2.3ps in vhdl. vhdl round off it to 2ps but i want 2.3ps in myopratins. tnx
Dear Friends, Kindly, I just started with vhdL, I need to display the numbers in the 7 segment display, I do not know how to solve this problem, I have an integer input and I need to display it. Always I face this message of error: (Error (10515): vhdL type mismatch error at ssd.vhd(18): bit type does not match string (...)
Hi, i have made one project in simulink (.mdl) just a 2x2 matrix multiply i used xilinx blockset toolbox for making 2x2 matirx multiply with the help of muliplier, add/subs, convert,gateway blocks etc. actually i am making a 32 bit width 2x2 matrix multiplier.. In model block of 2x2 matrix muliply ,the arrangement (connection of all ind
Hello,I want to import an array (1 x n) to my vhdl code,every element of array is 5-bit.I know I should be use it in serial but I dont know how define input "std_logic or std_logic_vector(4 downto 0)?
A vhdL file is source code and EDF file is a synthesised bit of code, hence why you cannot simulate it. You normally leave the block as a black box and add it in at the fitter stage.
how to solve this problem? "Error (10327): vhdL error at DU.vhd(51): can't determine definition of operator ""&"" -- found 0 possible definitions" my vhdL code is: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; . . ALU_module: process (selP, selQ, P, Q) variable sel: std_logic; begin
sir, i am fixed_pkg_c.vhd.during synthesis it gives error on alias statement.if i remove this "alias " only, it gives error ERROR:HDLParsers:164 - Line 1024. parse error, unexpected IDENTIFIER" the program copy whwre it gives the error is "function to_slv ( arg : UNRESOLVED_ufixed) -- fixed point vector return STD_LOGIC
You can open psm files with any text editor, the control.vhd was generated by picoblaze assembler that you can find in PicoBlaze source (from Xilinx download PicoBlaze), in the source you can find interesting things, like JTAG Loader. With JTAG Loader you can change the PicoBlaze program without regenerating the bit file. Depending your OS, can
you can create a 2 digit BCD counter by using two 4 bit counters and some logic gates.The main idea is that when the count in the first(LSB) counter reaches the value "1001"( 9 in decimal) it is reset to zero and the second(MSB) counter is incremented by '1'. I am not sure about why you need a 4:1 MUX for this. --vipin vhdlguru.blogspo
Hi I wrote some code for i2c and it works great write up to the point where i need to read information. The following code will start with start command >> address(read) >> command of register of interest >> another start command >> address(write) >> actuall reading of the register >> finally a stop command. -- sccb.vhd -- Initial
Hello Everybody, I need some help, and it's a little bit pressing I am co-simulating a design with vhdl - systemC I have a : 1) systemC file which generates stimuli (stimuli.h) 2) a vhdl source cordic_pipline.vhd 3) a top level file cordic.vhd which instanciate the latter ( (...)
Hi people, I want vhdL codes for implementing lowpass, highpass, bandpass and bandstop FIR digital filters. I am using Spartan 3 FPGA Board with built in 12 bit ADC and DAC sections. Can anyone plz give these codes to me or provide me with some link or method for implementing the same. My deadline is approaching n i need them urgently.
i didn't try ISE simulator. but for ModelSim, you can simulate them in the following order and it will work: alusel.vhd cntrpipe.vhd pcimem.vhd rfcache.vhd toprisc.vhd if you still have problems, pls post the error msgs for analysis.
Checkout this .....
hi all i am using this function to convetr integer to bitvector and Synplify gives error pack.vhd(25): type bit needs a syn_enum_encoding attribute of "sequential" @E:"c:\synthesis\one\pack.vhd":25:22:25:29 code is here:- please have a look ------------------------------------------------------------------- (...)
Hi all I designed and implement a 4 bit adder which gets a carrier bit as an input, adds up two 4 bit numbers, and gives a 4 bit number and a carrier bit as outputs in vhdL. What is vhdl code?
Hi all. Sorry, but this is most likely a device core. You can tell from line 74 of pdiusb.vhd: "Reset from host detect" A host would never need to detect a reset condition on the bus since only the host can assert a bus reset. Also, the design is a bit simplistic for a host controller. Many basic things are not present such as SOF generation