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## How to make circuit two multiply two numbers.

Use an FPGA and write vhdl/Verilog.. e.g. mult_result <= a * b; add_result <= a + b;

## Analizing a VHDL program code

Hi there, I am new to this forum as well as i am new to vhdl. Teacher gave as a test to do at home and i have struggles with one of the test. We got a code and our task is to analyze it and write down the purpose of the Device. We also have to explain the the purpose of parameter s and out_sig, in_sig, mode, clk ports. What i see is that we

## Width of result vector in VHDL

Multiplication will yield bit growth on more occasions then addition - but it isn't guarantied. Some examples: "0100" * "0010" = "1000" "1111" * "0001" = "1111" An example for what? It has nothing to do with the bit width of an unsigned vhdl multiply operation which doesn't depend on a particular number value. You'll fin

## Full adder with 3 input signals (vectors)

If you're going to use addition just for the carries, why not go the whole hog and just make your life easy and use + for the whole adder? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity full_adder_12bit is port ( a : in unsigned(11 downto 0); b : in unsigned(11 downto 0); c : out unsigned(1

## fixed point addition and multiplication in VHDL for Xilinx FPGA

Hi All, I have to implement a tapped FIR filter which has fixed point coefficients. I am considering using the proposed IEEE fixed point package. From what I have read on Xilnx and edaboard forums the package does not seem to give correct synthesizable results and/or is not well supported. I am not sure if these issues are fixed or not. I

Hi. I will explain my problem simply. I'm trying to get summary of 4-bit vectors in one, 8-bit vector. signal cnt1,cnt2,cnt3,cnt4,cnt5 : STD_LOGIC_VECTOR (3 downto 0); signal count : STD_LOGIC_VECTOR (7 downto 0); cnt1 <= "0000"; cnt2 <= "0000"; cnt3 <= "0000"; cnt4 <= "0001"; cnt5 <= "1111"; count <= cnt1

## Xilinx Device utilization

vhdl -> generics Verilog -> parameters Read up on this...

## VHDL signed numbers arithmetics

My FPGA is communicating with an ADC over a serial bus. The ADC supports negative voltage readings. Figure 26 at page 14 suggests that the device uses the leftmost bit as the sign bit. I'm required to calculate the algebraic sum of 32 consecutive readings. As you explaine

## VHDL inner component with inout port

Just tried it with this code: library ieee; use ieee.std_logic_1164.all; entity a is port (x : inout std_logic); end entity; architecture behave of a is signal z : std_logic; begin z <= not x; end architecture behave; library ieee; use ieee.std_logic_1164.all; entity b is port (y : inout std_logic); end e

## Expression evaluation in vhdl and verilog

hi , How verilog and vhdl expressions are evaluated.i am getting different results when the same code is written in verilog and vhdl. the expression is: d=(a+b)*p; a,b,p are signed numbers of size 16 bits and d is the signed number with 32 bits.when a, b are 16384(decimal numbers) and p is 1229 .The vhdl simulator is giving output as (...)

## Unsigned and Signed Addition and subtraction VHDL

Hi all! I am trying to design an ALU which does signed addition & subtraction and unsigned addition & subtraction. I have following code written, but does not work. For unsigned : I used simple R<= A+B and R<= A-B; for addition and subtraction For Signed: I tried to change the type of A,B to Signed and perform addition. (...)

## vhdl file handling......................

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use std.textio.all; entity rom_using_file is GENERIC (N :INTEGER:=260); port ( ce,clk ,clk1,read :in std_logic; -- Chip Enable read_en :in std_logic;

## help a noob - VHDL code

It's not clear what you mean with "varied bit length" and why it should be used in the vhdl example. The addition std_logic_vector(unsigned(A) + unsigned(B)); has a 4-bit result width according to vhdl rules. There won't be a problem however to generate a carry in the addition and get a 5 bits wide result. One (...)

## problem in an addition in a vhdl code

From this code - I guess you have a software background? There is a major problem with the code in that the process is sensitive to a signal that is updated inside itself - so this process will just run in an infinite loop in simulation and you'll probably hit the iteration limit. Initialisation is that - the value given to a signal/variable when

## Implementation of radix 2 FFT with Cordic in VHDL

I am implementing radix 2 FFT of 8 point in vhdl.During this project i faced the problem of complex addition,subtraction and multiplication.i have also written a code for FFT but that is containing the error of complex part.although ready made ip core is available but i have to write the code.for the sake of my understanding i have implemented the

## Implementation of FFT

For Implementation of 8 point radix 2 FFT butterfly structure is cordic needed for realization of its structure or just a complex multiplier is sufficient to solve the problem of complex addition and subtraction in vhdl.

## nxm SHIFT REGISTER IMPLEMANTATION BY VHDL

Hello everybody , i am doing a shift register project that operates "n x m" bit . Here "m" is bitwith, "n" is number of "m's". I handled my projeck by sampling register using Flipflops and achieved it. Register section works well. Now i have to multiply register "n" times . here i have some difficulties and i have two subtle erros . What could b

## Problem with simple 4-bit adder vhdl code

c <= ('a(3)'&a) + ('b(3)'&b);--to make sign extension. You can also write c <= resize(a,5) + resize(b,5); or even shorter c <= resize(a,5) + b; What I'm doing is because vhdl imposes that the LHS to the equal sign of addition is the same size as the RHS' operands. Will this concatenated bit be r

## FFT butterfly structure

I am implementing the FFT butterfly structure.For that purpose i need complex addition,multiplication and subtraction in vhdl.The program is running fine but while simulating its showing error that the product value is out of range,what should i do now......please anyone help me in this regard